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| CXD3511AQ Digital Signal Driver/Timing Generator Description The CXD3511AQ incorporates digital signal processor type RGB driver, color shading correction, selectable delay line and timing generator functions onto a single IC. Operation is possible with a system clock up to 200 [MHz] (max.). This IC can process video signals in bands up to UXGA standard, and can output the timing signals for driving various Sony LCD panels such as UXGA, SXGA and XGA. Features * Various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction * OSD MIX, black frame processing, mute and limiter functions * LCD panel color shading correction function * Selectable delay line * Drives various Sony data projector LCD panels such as UXGA, SXGA and XGA * Controls the CXA3562AR and CXA7000R sampleand-hold drivers * Line inversion and field inversion signal generation * Supports AC drive of LCD panels during no signal Applications LCD projectors and other video equipment Structure Silicon gate CMOS IC 240 pin QFP (Plastic) Absolute Maximum Ratings (VSS = 0V) * Supply voltage VDD1 VSS - 0.5 to +3.0 V VDD2 VSS - 0.5 to +4.0 V * Input voltage VI VSS - 0.5 to VDD1 + 0.5 V * Output voltage VO VSS - 0.5 to VDD1 + 0.5 V * Storage temperature Tstg -55 to +125 C * Junction temperature Tj 125 C Recommended Operating Conditions 2.3 to 2.7 * Supply voltage VDD1 VDD2 3.0 to 3.6 * Operating temperature Topr -20 to +75 V V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E02401-PS CXD3511AQ Block Diagram R, G, B IN R, G, B OSD YM YS 8x2x3 2x2x3 2 2 DSD 10 x 2 x 3 R, G, B OUT PCTL PCLK PDAT 10 CLKOUT PARALLEL I/F PLL TG CTRL RGT, DWN PCG, BLK, HST, ENBR, ENBL, VSTR, VSTL, VCKR, VCKL, HCK1, DCK1, DCK2, HCK2, DCK1X, DCK2X, XRGT, FRP, XFRP, PRG, DENB, CLP, PO1, PO2, PO3, PO4, PO5, PST, HD1, HD2 CLKC CLKP CLKN CLKSEL1 CLKSEL2 PLLDIV HDIN VDIN DQ Q Direct Clear XCLR1 XCLR2 XCLR3 -2- CXD3511AQ Pin Configuration R2OUT9 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 R1IN2 181 R1IN1 182 R1IN0 183 R2IN7 184 R2IN6 185 VDD2 186 VSS 187 R2IN5 188 R2IN4 189 R2IN3 190 R2IN2 191 R2IN1 192 R2IN0 193 G1IN7 194 G1IN6 195 G1IN5 196 VDD1 197 VSS 198 G1IN4 199 G1IN3 200 G1IN2 201 G1IN1 202 G1IN0 203 G2IN7 204 G2IN6 205 G2IN5 206 G2IN4 207 G2IN3 208 VDD1 209 VSS 210 G2IN2 211 G2IN1 212 G2IN0 213 B1IN7 214 B1IN6 215 B1IN5 216 B1IN4 217 B1IN3 218 B1IN2 219 B1IN1 220 VDD1 221 VSS 222 B1IN0 223 B2IN7 224 B2IN6 225 B2IN5 226 B2IN4 227 B2IN3 228 B2IN2 229 B2IN1 230 B2IN0 231 R1OSD1 232 R1OSD0 233 VDD2 234 VSS 235 G1OSD1 236 G1OSD0 237 B1OSD1 238 B1OSD0 239 YM1 240 R1OUT8 DCK1X DCK2X TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 XRGT DENB ENBR VCKR XFRP HCK2 HCK1 DCK1 DCK2 VSTR SHST VCKL ENBL CTRL VSTL DWN VDD2 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 PRG PCG RGT PO5 PO4 PO1 PO2 PO3 FRP HD1 HD2 HST CLP PST BLK VSS VSS VSS VSS VSS VSS VSS 120 R1OUT7 119 R1OUT6 118 R1OUT5 117 R1OUT4 116 R1OUT3 115 VSS 114 VDD2 113 R1OUT2 112 R1OUT1 111 R1OUT0 110 R2OUT9 109 R2OUT8 108 R2OUT7 107 R2OUT6 106 R2OUT5 105 R2OUT4 104 R2OUT3 103 R2OUT2 102 VSS 101 VDD1 100 VDD2 99 R2OUT1 98 R2OUT0 97 G1OUT9 96 G1OUT8 95 G1OUT7 94 G1OUT6 93 G1OUT5 92 G1OUT4 91 G1OUT3 90 VSS 89 VDD1 88 G1OUT2 87 G1OUT1 86 G1OUT0 85 G2OUT9 84 VDD2 83 G2OUT8 82 G2OUT7 81 G2OUT6 80 G2OUT5 79 G2OUT4 78 VSS 77 VDD1 76 G2OUT3 75 G2OUT2 74 G2OUT1 73 G2OUT0 72 B1OUT9 71 B1OUT8 70 B1OUT7 69 B1OUT6 68 B1OUT5 67 VSS 66 VDD2 65 B1OUT4 64 B1OUT3 63 B1OUT2 62 B1OUT1 61 B1OUT0 1 YS1 2 R2OSD1 3 R2OSD0 4 G2OSD1 5 G2OSD0 6 VDD2 7 VSS 8 B2OSD1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VDD2 VDD1 VDD1 VDD1 VDD2 VDD1 VDD2 VSS VSS VSS VSS VSS VSS VSS HDIN VDIN CLKSEL1 CLKSEL2 CLKOUT B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 VSS B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OSD0 B2OUT9 YM2 YS2 PCTL PCLK PDAT9 PDAT8 PDAT7 PDAT6 PLLDIV PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 XCLR1 XCLR2 XCLR3 CLKC CLKP CLKN -3- CXD3511AQ Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol YS1 R2OSD1 R2OSD0 G2OSD1 G2OSD0 VDD2 VSS B2OSD1 B2OSD0 YM2 YS2 PCTL PCLK PDAT9 PDAT8 PDAT7 PDAT6 VDD2 VSS PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 VDD1 PDAT0 XCLR1 XCLR2 XCLR3 VSS HDIN VDIN VSS VSS CLKC VDD1 VDD1 I/O I I I I I -- -- I I I I I I I I I I -- -- I I I I I -- I I I I -- I I -- -- I -- -- OSD YS input (port 1) OSD Red data input (port 2) OSD Red data input (port 2) OSD Green data input (port 2) OSD Green data input (port 2) I/O power supply GND OSD Blue data input (port 2) OSD Blue data input (port 2) OSD YM input (port 2) OSD YS input (port 2) Parallel I/F control signal input Parallel I/F clock input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input I/O power supply GND Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Internal operation power supply Parallel I/F data input External clear (Low: reset) External clear (Low: reset) External clear (Low: reset) GND Horizontal sync signal input Vertical sync signal input GND GND Clock input (CMOS input) Internal operation power supply Internal operation power supply -4- -- -- -- -- -- -- -- -- H H H -- -- -- -- -- -- -- -- Description Input pin processing for open status L -- -- -- -- -- -- -- -- L L H -- -- -- -- -- CXD3511AQ Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Symbol CLKP CLKN VDD2 CLKSEL1 VDD1 VSS CLKSEL2 PLLDIV VSS CLKOUT VSS B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 VDD2 VSS B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OUT9 B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 VDD2 VSS B1OUT5 B1OUT6 B1OUT7 B1OUT8 B1OUT9 G2OUT0 G2OUT1 I/O I I -- I -- -- I I -- O -- O O O O O -- -- O O O O O O O O O O -- -- O O O O O O O Description Clock input (small-amplitude differential input, positive polarity) Clock input (small-amplitude differential input, negative polarity) I/O power supply Input clock selection. (High: CLKC, Low: CLKP CLKN) , Internal operation power supply GND Internal clock path selection. (High: no frequency division, Low: frequency division) Internal PLL setting. (High: 55MHz or less, Low: 55MHz or more) GND Internal clock output (inverted output) GND Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) I/O power supply GND Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) I/O power supply GND Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Green data output (port 2) Green data output (port 2) -5- Input pin processing for open status -- -- -- L -- -- L L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD3511AQ Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 Symbol G2OUT2 G2OUT3 VDD1 VSS G2OUT4 G2OUT5 G2OUT6 G2OUT7 G2OUT8 VDD2 G2OUT9 G1OUT0 G1OUT1 G1OUT2 VDD1 VSS G1OUT3 G1OUT4 G1OUT5 G1OUT6 G1OUT7 G1OUT8 G1OUT9 R2OUT0 R2OUT1 VDD2 VDD1 VSS R2OUT2 R2OUT3 R2OUT4 R2OUT5 R2OUT6 R2OUT7 R2OUT8 R2OUT9 R1OUT0 I/O O O -- -- O O O O O -- O O O O -- -- O O O O O O O O O -- -- -- O O O O O O O O O Description Green data output (port 2) Green data output (port 2) Internal operation power supply GND Green data output (port 2) Green data output (port 2) Green data output (port 2) Green data output (port 2) Green data output (port 2) I/O power supply Green data output (port 2) Green data output (port 1) Green data output (port 1) Green data output (port 1) Internal operation power supply GND Green data output (port 1) Green data output (port 1) Green data output (port 1) Green data output (port 1) Green data output (port 1) Green data output (port 1) Green data output (port 1) Red data output (port 2) Red data output (port 2) I/O power supply Internal operation power supply GND Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 1) -6- Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD3511AQ Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 Symbol R1OUT1 R1OUT2 VDD2 VSS R1OUT3 R1OUT4 R1OUT5 R1OUT6 R1OUT7 R1OUT8 R1OUT9 VSTR VCKR ENBR VDD2 VSS DCK2 DCK2X VSS DCK1X DCK1 VSS HCK1 HCK2 RGT XRGT VDD2 VSS HST BLK ENBL VCKL VDD2 VDD1 VSTL DWN I/O O O -- -- O O O O O O O O O O -- -- O O -- O O -- O O I/O O -- -- O O O O -- -- O I/O Red data output (port 1) Red data output (port 1) I/O power supply GND Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Vertical display start timing pulse output Vertical display transfer clock output Gate enable pulse output I/O power supply GND DCK2 pulse output DCK2X pulse output GND DCK1X pulse output DCK1 pulse output GND Horizontal display transfer clock output 1 Horizontal display transfer clock output 2 Horizontal scan direction switching signal I/O Horizontal scan direction switching signal output (reversed polarity of RGT) I/O power supply GND Horizontal display start timing pulse output BLK pulse output Gate enable pulse output Vertical display transfer clock output I/O power supply Internal operation power supply Vertical display start timing pulse output Vertical scan direction switching signal I/O -7- CXD3511AQ Pin No. 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Symbol CTRL PCG VSS PST PO3 PO2 PO1 HD2 VDD1 FRP XFRP SHST DENB PRG VDD1 VSS PO4 CLP PO5 HD1 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 VDD2 VSS R1IN7 R1IN6 R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN7 I/O I O -- O O O O O -- O O O O O -- -- O O O O -- -- -- -- -- -- -- -- I I I I I I I I I Description Scan direction control method switching (Low: internal register, High: external) Collective precharge timing pulse output GND Dot sequential precharge start timing pulse output Parallel output 3 Parallel output 2 Parallel output 1 Horizontal auxiliary pulse output 2 Internal operation power supply AC drive inversion timing pulse output AC drive inversion timing pulse output (reversed polarity of FRP) SHST pulse output DENB pulse output 2-step precharge timing pulse output Internal operation power supply GND Parallel output 4 CLP pulse output Parallel output 5 Horizontal auxiliary pulse output 1 Test pin (Connect to GND.) Test pin (Connect to GND.) Test pin (Connect to VDD1.) Test pin (Connect to VDD1.) Test pin (Connect to VDD1.) Test pin (Connect to VDD1.) I/O power supply GND Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 2) -8- Input pin processing for open status L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD3511AQ Pin No. 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 Symbol R2IN6 VDD2 VSS R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 G1IN7 G1IN6 G1IN5 VDD1 VSS G1IN4 G1IN3 G1IN2 G1IN1 G1IN0 G2IN7 G2IN6 G2IN5 G2IN4 G2IN3 VDD1 VSS G2IN2 G2IN1 G2IN0 B1IN7 B1IN6 B1IN5 B1IN4 B1IN3 B1IN2 B1IN1 VDD1 I/O I -- -- I I I I I I I I I -- -- I I I I I I I I I I -- -- I I I I I I I I I I -- Red data input (port 2) I/O power supply GND Red data input (port 2) Red data input (port 2) Red data input (port 2) Red data input (port 2) Red data input (port 2) Red data input (port 2) Green data input (port 1) Green data input (port 1) Green data input (port 1) Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Internal operation power supply GND Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 2) Green data input (port 2) Green data input (port 2) Green data input (port 2) Green data input (port 2) Internal operation power supply GND Green data input (port 2) Green data input (port 2) Green data input (port 2) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Internal operation power supply -9- CXD3511AQ Pin No. 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VSS B1IN0 B2IN7 B2IN6 B2IN5 B2IN4 B2IN3 B2IN2 B2IN1 B2IN0 R1OSD1 R1OSD0 VDD2 VSS G1OSD1 G1OSD0 B1OSD1 B1OSD0 YM1 I/O -- I I I I I I I I I I I -- -- I I I I I GND Blue data input (port 1) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L OSD red data input (port 1) OSD red data input (port 1) I/O power supply GND OSD green data input (port 1) OSD green data input (port 1) OSD blue data input (port 1) OSD blue data input (port 1) OSD YM input (port 1) H: Pull-up, L: Pull-down - 10 - CXD3511AQ Electrical Characteristics DC Characteristics Item Supply voltage Input voltage 1 Input voltage 2 Input voltage 3 Output voltage Current consumption Symbol VDD1 VDD2 VIH1 VIL1 VIH2 VIL2 VC2 VIH3 VIL3 VOH VOL PD3 All output pins -- -- -- CLKP = 200MHz 1 Applicable pins -- -- -- CMOS input cell Conditions (Topr = -20 to +75C, VSS = 0V) Min. 2.3 3.0 2.0 -0.3 0.8VDD2 -0.3 1.718 CLKP CLKN , Small-amplitude differential input 1.868 VSS VDD2 - 0.5 VSS -- Typ. 2.5 3.3 -- -- -- -- 2.0 VC + 0.4 VC - 0.4 -- -- 2600 Max. 2.7 3.6 VDD2 + 0.3 0.8 VDD2 + 0.3 0.2VDD2 2.281 VDD2 2.131 VDD2 0.2 3120 mW V Unit HDIN, VDIN, PCTL, CMOS Schmitt PCLK, PDAT0 to PDAT9 trigger input cell 1 Input pins other than those indicated in items Input voltage 2 and Input voltage 3. 2 VIH3 > VC (max.) and VIL3 < VC (min.). 3 Tj [C] Toprmax [C] + ja [C/W] x PD [W]. (Tj = 125 [C], Toprmax = 75 [C], ja = 16 [C/W], when mounted on a 4-layer substrate) AC Characteristics Item Clock input period Input setup time Input hold time Output rise/fall delay time Output rise/fall delay time Cross-point time difference HCK1 duty HCK2 duty Phase compensation PLL operating frequency Symbol -- (Topr = -20 to +75C, VDD1 = 2.5 0.2V, VDD2 = 3.3 0.3V, VSS = 0V) Applicable pins CLKP CLKN, CLKC , RGB input, OSD input, HDIN, VDIN 4 CLKOUT HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X HCK1 HCK2 -- PLLDIV = H 27.5 -- 55 Conditions -- -- -- CL = 20pF CL = 50pF CL = 20pF CL = 20pF CL = 20pF PLLDIV = L -- Min. 5 2.5 1.5 2.0 2.5 -5.0 48 48 55 Typ. -- -- -- 4.0 4.5 -- 50 50 -- Max. -- -- -- 8.0 8.5 5.0 52 52 100 MHz % ns Unit tis tih tor/tof tor/tof t th/(th + tl) tl/(th + tl) 4 Output pins other than CLKOUT, PO1 to PO5, RGT, XRGT and DWN. - 11 - CXD3511AQ Power-on and Initialization of Internal Circuit As for this IC, two systems of supply voltage should be turned on simultaneously. The initialization of the internal circuit should be also performed by maintaining the system clear pin at low during the specified time after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in the figure below. Keep in mind that the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply voltage is set in the range of the recommended operating conditions. VDD1, VDD2 VDD1, VDD2 Vss XCLR1, XCLR2, XCLR3 TR TR > 200ns VDD2 Vss - 12 - CXD3511AQ Timing Definition VIH3, VDD2 CLKP, CLKC VC, 50% VIL3, VSS VIH3 CLKN CLKP, CLKC 1/2 frequencydivided inputs CLKN RGB input, OSD input, HDIN, VDIN tis tih 50% VIL3 VDD2 VSS VC VIL3 VIH3, VDD2 VC, 50% VIL3, VSS VIH3 VIH3, VDD2 CLKP, CLKC VC, 50% VC, 50% VIL3, VSS VIH3 CLKN VC VC VIL3 VIH3, VDD2 CLKP, CLKC VC, 50% 1/2 frequencydivided inputs CLKN CLKOUT tof Outputs other than CLKOUT tor VDD2 Outputs other than CLKOUT tof 50% VSS 50% VSS VC VC VIL3 VDD2 50% tor 50% VSS VDD2 VC, 50% VIL3, VSS VIH3 VDD2 HCK1, DCK1, DCK2 50% 50% VSS VDD2 HCK2, DCK1X, DCK2X t 50% t VDD2 HCK1, HCK2 50% th 50% tl 50% VSS 50% VSS - 13 - CXD3511AQ Parallel I/F Block AC Characteristics (Topr = -20 to +75C, VDD1 = 2.5 0.2V, VDD2 = 3.3 0.3V, VSS = 0V) Item PCTL setup time with respect to rise of PCLK PCTL hold time with respect to rise of PCLK PDAT[9:0] setup time with respect to rise of PCLK PDAT[9:0] hold time with respect to rise of PCLK PCLK pulse width 5 T: Master clock (CLKP CLKN, CLKC) period [ns] , Timing Definition tcs PCTL 50% tw PCLK 50% tds PDAT[9:0] 50% tdh VDD2 50% VSS tw VDD2 50% VSS tch VDD2 50% VSS Symbol tcs tch tds tdh tw Min. 8T5 8T 4T 4T 4T Typ. -- -- -- -- -- Max. -- -- -- -- -- - 14 - CXD3511AQ Description of Operation 1. Description of Input Pins (a) System clear pins (XCLR1, XCLR2 and XCLR3) All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low. Initialization should be performed when power is turned on. There are no particular restrictions on the initialization order. (b) Sync signal input pins (HDIN and VDIN) Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The CXD3511AQ supports only non-interlace sync signals with a dot clock of 200MHz or less. (c) Master clock input pins (CLKP/CLKN and CLKC) Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude differential input (center level: 2.0V, amplitude: 0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be sure to make the number of dot clocks in 1H as even number. Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate properly. (d) Clock selection pins (CLKSEL1 and CLKSEL2) The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44). Setting L CLKP/CLKN input Dot clock input CLKC input 1/2 frequency-divided clock input H Symbol CLKSEL1 CLKSEL2 Function Input clock selection Clock input pin selection (e) PLL setting pin (PLLDIV) PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency of the clock input to the CXD3511AQ must be within the phase compensation PLL operating range, even during free running. - 15 - CXD3511AQ (f) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN) These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 176 to 183) and R2IN (Pins 184, 185 and 188 to 193), the Green signal to G1IN (Pins 194 to 196 and 199 to 203) and G2IN (Pins 204 to 208 and 211 to 213), and the Blue signal to B1IN (Pins 214 to 220 and 223) and B2IN (Pins 224 to 231). (g) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2) These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins 232 and 233) and R2OSD (Pins 2 and 3), the Green signal to G1OSD (Pins 236 and 237) and G2OSD (Pins 4 and 5), and the Blue signal to B1OSD (Pins 238 and 239) and B2OSD (Pins 8 and 9). In addition, the YM signal is input to YM1 (Pin 240) and YM2 (Pin 10), and the YS signal to YS1 (Pin 1) and YS2 (Pin 11). - 16 - CXD3511AQ 2. RGB Signal and OSD Signal Pipeline Delay The RGB signal I/O pipeline delay is 72 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 56 dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the figures below. This relationship is the same for the OSD, YM and YS signals. (1) CLKPOL = L HDIN input (negative polarity) Dot clock 1/2 frequency-divided clock R1, G1, B1IN R2, G2, B2IN CLKOUT R1, G1, B1OUT R2, G2, B2OUT N - 74 N - 72 N - 70 N - 68 N - 66 N - 64 N - 62 N - 60 N - 58 N - 56 N - 54 N - 73 N - 71 N - 69 N - 67 N - 65 N - 63 N - 61 N - 59 N - 57 N - 55 N - 53 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19 (2) CLKPOL = H HDIN input (negative polarity) Dot clock 1/2 frequency-divided clock R1, G1, B1IN R2, G2, B2IN CLKOUT R1, G1, B1OUT R2, G2, B2OUT N - 74 N - 72 N - 70 N - 68 N - 66 N - 64 N - 62 N - 60 N - 58 N - 56 N - 54 N - 73 N - 71 N - 69 N - 67 N - 65 N - 63 N - 61 N - 59 N - 57 N - 55 N - 53 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19 - 17 - CXD3511AQ 3. Description of DSD Block Signal Processing Functions The DSD block signal processing flow is shown below. R, G, B IN Data path switch Pre gain Pre bright User gain User bright Sub gain YS, YM, R, G, B OSD Sub bright Black frame Mute 1 Pattern generator OSD Gamma correction Color shading correction Selectable delay line Mute 2 Limiter Post gain Post bright Ghost cancel Cycle offset R, G, B OUT The various signal processing functions are described below. Note that the coefficients used for each arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F block item for a detailed description of the parallel I/F block. (a) Data path switch block This block can switch the path of the data input to ports 1 and 2. The setting is as follows. Select signal: 1 = Path switched, 0 = Path not switched (Set independently for R, G and B) Select signal (R, G, B_DAT_SW) Input (port 1) Input (port 2) 8 8 Selector 8 Output (port 1) Selector 8 Output (port 2) - 18 - CXD3511AQ (b) Pre gain block This block performs calculation processing independently for ports 1 and 2. The settings are as follows. Coefficient: 8 bits Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps (Set independently for R, G and B ports 1 and 2) Calculation is performed using the 8-bit input and an 8-bit coefficient, and the upper 10 bits c[15:6] of the operation results are output. Next, the c[6] value is checked and rounding is performed to 9 bits. The MSB of the rounded 9 bits is checked, clipping is performed, and the lower 8 bits are output. Coefficient 8 b[7:0] Input a[7:0] 8 10 c[15:6] Rounding and clipping 8 axb Output (c) Pre bright block This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as follows. Coefficient: 5 bits with code, MSB = code bit Bright setting: -16 to +15 graduation, variable with an accuracy of 1 bit (Set independently for R, G and B ports 1 and 2) Calculation is performed using the 8-bit input and a 5-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[4] = 0, and subtraction when b[4] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Coefficient 5 b[4:0] Input a[7:0] 8 Addition/subtraction and clipping 8 Output (d) User gain block This block performs calculation processing independently for ports 1 and 2. The settings are as follows. Coefficient: 8 bits Gain setting: 0 to 7.96875 (= 255/32) times, variable in 256 steps (Settings shared by R, G and B) Calculation is performed using the 8-bit input and an 8-bit coefficient, and the upper 12 bits c[15:4] of the operation results are output. Next, the c[4] value is checked and rounding is performed to 11 bits. The MSB of the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output. Coefficient 8 b[7:0] Input a[7:0] 8 12 c[15:4] Rounding and clipping 10 axb Output - 19 - CXD3511AQ (e) User bright block This block performs addition and subtraction processing as the user control bright adjustment. The settings are as follows. Coefficient: 11 bits with code, MSB = code bit Bright setting: -1024 to +1023 graduation, variable with an accuracy of 1 bit (Settings shared by R, G and B) Calculation is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Coefficient 11 b[10:0] Input 10 a[9:0] Addition/subtraction and clipping 10 Output (f) Sub gain block This block performs calculation processing as the white balance gain adjustment. The settings are as follows. Coefficient: 8 bits Gain setting: 0 to 3.984375 (255/64) times, variable in 256 steps (Set independently for R, G and B) Calculation is performed using the 10-bit input and an 8-bit coefficient, and the upper 13 bits c[17:5] of the operation results are output. Next, the c[5] value is checked and rounding is performed to 12 bits. The upper 2 bits of the rounded 12 bits is checked, clipping is performed, and the lower 10 bits are output. Coefficient 8 b[7:0] Input 10 a[9:0] 13 c[17:5] Rounding and clipping 10 axb Output (g) Sub bright block This block performs addition and subtraction processing as the white balance bright adjustment. The settings are as follows. Coefficient: 11 bits with code, MSB = code bit Bright setting: -1024 to +1023 graduation, variable with an accuracy of 1 bit (Set independently for R, G and B) Calculation is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Coefficient 11 b[10:0] Input 10 a[9:0] Addition/subtraction and clipping 10 Output - 20 - CXD3511AQ (h) Black frame block This block performs processing to fix the blanking period of the video signal to the desired level regardless of the front-end signal processing results. If the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the LCD panel on which the signal is to be displayed, the blanking period of the video signal is displayed in the excess pixels. At this time, the displayed blanking period can be fixed to the desired level regardless of the gain and bright adjustment or other picture quality adjustment results by processing with this block. The settings are as follows. FRM_ON: 1 = Black frame processing ON, 0 = OFF FRM_DAT: Black frame level setting FRM_H1, FRM_H2: Set the black frame horizontal display range in 1-dot units FRM_V1, FRM_V2: Set the black frame vertical display range in 1-line units (All settings shared by R, G and B) Here, the desired range of the video signal is replaced with 10-bit data (FRM_DAT) by switching the video signal (port 1 and port 2) and the coefficients using the pulse output from the pulse decoder. 12 Internal HD Internal VD Internal MCLK Processing ON/OFF (FRM_ON) Input (port 1) Coefficient (FRM_DAT) 10 10 Selector 10 Output (port 1) Pulse decoder 12 11 11 Horizontal display range (FRM_H1) Horizontal display range (FRM_H2) Vertical display range (FRM_V1) Vertical display range (FRM_V2) Input (port 2) 10 Selector 10 Output (port 2) (i) Mute 1 block This block performs mute processing by replacing the video signal with data of the desired level. The settings are as follows. MUTE1_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B) R, G, B_MUTE1: RGB mute data (Set independently for R, G and B) Select signal (MUTE1_ON) Input Coefficient (R, G, B_MUTE1) 10 10 Selector 10 Output - 21 - CXD3511AQ (j) Pattern generator block This block generates and outputs the set fixed pattern independently of the input signal. This function is valid when PG_ON = 1. When PG_R (G, B)_ON is "0", the signal level goes to 000h respectively for R, G and B. The raster display pattern is displayed in the effective area, and all other display patterns are displayed in the window area. Here, the effective area is set by PG_HST, PG_HSTP, PG_VST and PG_VSTP and the window , area is set by PG_HWST, PG_HWSTP PG_VWST and PG_VWSTP , . The display pattern signal level is set independently for R, G and B by PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0]. Within the effective area, the pattern and non-pattern signal levels can be switched by PG_R (G, B)_SEL. At this time, the signal level outside the effective area goes to 000h. During horizontal ramp, horizontal stair, vertical ramp and vertical stair display, the PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are invalid. The display patterns and signal levels are as follows. (1) Raster display When PG_PAT[2:0] = 0h, a raster is displayed. PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_SIG2R (G, B) 0 0h x x PG_STAIR_SW PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_SIG1R (G, B) 1 0h x x PG_STAIR_SW x: Don't care - 22 - CXD3511AQ (2) Window display When PG_PAT[2:0] = 1h, a window is displayed. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 1h x x PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 1h x x PG_SIG2R (G, B) x: Don't care - 23 - CXD3511AQ (3) Vertical stripe display When PG_PAT[2:0] = 2h and PG_STRP_SW = 0, vertical stripes are displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 2h 0 x PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 2h 0 x PG_SIG2R (G, B) x: Don't care - 24 - CXD3511AQ (4) Diagonal stripes When PG_PAT[2:0] = 2h and PG_STRP_SW = 1, diagonal stripes are displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_R (G, B)_SEL PG_SIG2R (G, B) 0 2h 1 x PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 2h 1 x PG_SIG2R (G, B) x: Don't care - 25 - CXD3511AQ (5) Horizontal stripes When PG_PAT[2:0] = 3h, horizontal stripes are displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 3h x x PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 3h x x PG_SIG2R (G, B) x: Don't care - 26 - CXD3511AQ (6) Cross hatch When PG_PAT[2:0] = 4h, a cross hatch is displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 4h x x PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 4h x x PG_SIG2R (G, B) x: Don't care - 27 - CXD3511AQ (7) Dots When PG_PAT[2:0] = 5h, a dot pattern is displayed. The dot period is set by PG_STEP in 2-dot units. The dot width is set by PG_WIDTH in 1-dot units. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 5h x x PG_SIG1R (G, B) PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 5h x x PG_SIG2R (G, B) x: Don't care - 28 - CXD3511AQ (8) Horizontal ramp When PG_PAT[2:0] = 6h and PG_STAIR_SW = 0, a horizontal ramp is displayed. The signal level is incremented from 000h by one bit for each dot. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 6h x 0 PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 6h x 0 x: Don't care - 29 - CXD3511AQ (9) Horizontal stair When PG_PAT[2:0] = 6h and PG_STAIR_SW = 1, a horizontal stair is displayed. The signal level is incremented from 000h by 64 bits for each 64 dots. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 6h x 1 PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 6h x 1 x: Don't care - 30 - CXD3511AQ (10) Vertical ramp When PG_PAT[2:0] = 7h and PG_STAIR_SW = 0, a vertical ramp is displayed. The signal level is incremented from 000h by one bit for each line. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 7h x 0 PG_SIG1R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 1 7h x 0 x: Don't care - 31 - CXD3511AQ (11) Vertical stair When PG_PAT[2:0] = 7h and PG_STAIR_SW = 1, a vertical stair is displayed. The signal level is incremented from 000h by 64 bits for each 32 lines. PG_SIG2R (G, B) PG_R (G, B)_SEL PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW 0 7h x 1 PG_R (G, B)_SEL PG_SIG1R (G, B) 1 7h x 1 PG_PAT[2:0] PG_STRP_SW PG_STAIR_SW x: Don't care - 32 - CXD3511AQ (k) OSD block This block performs video signal half-tone processing and OSD-MIX processing by inputting the 2-bit OSD signal for each color and the YS and YM signals. The half-tone processing setting is as follows. YM signal input: 1 = Half-tone processing ON, 0 = OFF Here, the video signal level is halved by shifting the input data by one bit to the LSB side when YM = 1. For example, when 0F0h is input, 078h is output. The selector selects one of four types of data with respect to the OSD signal value as shown in the table below. The selected data becomes the OSD signal gradual data. The selected gradual data can be set independently in 10 bits for R, G and B, so 4 graduation can be selected as desired from among 1024 graduation for each of R, G and B. Therefore, the desired 64 (= 2^6) colors can be selected from among the total 1.07374 billion (= 2^30) colors for R, G and B. OSD signal input 0h 1h 2h 3h Selected gradual data R, G, B_OSD_DAT1 R, G, B_OSD_DAT2 R, G, B_OSD_DAT3 R, G, B_OSD_DAT4 The OSD-MIX processing setting is as follows. YS signal input: 1 = OSD-MIX processing ON, 0 = OFF OSD signal Gradual data (R, G, B_OSD_DAT1) Gradual data (R, G, B_OSD_DAT2) Gradual data (R, G, B_OSD_DAT3) Gradual data (R, G, B_OSD_DAT4) YS signal YM signal 10 2 10 10 10 10 Selector 10 Input Half-tone processing 10 OSD-MIX 10 Output - 33 - CXD3511AQ (l) Gamma block This block performs gamma correction for the user- and white balance-adjusted signal. Gamma correction uses the LUT system, and the RAM size is 10 bits x 1024 words. The settings are as follows. GAM_ON: 1 = Normal operation, 0 = Standby mode GAM_SEL: 1 = Path passing through the RAM, 0 = Path not passing through the RAM (All settings shared by R, G and B) When operating the RAM, be sure to set GAM_ON = 1. Data cannot be written to or read from the RAM in standby mode. The RAM data is set through the parallel I/F block. Note that the RAM output is undetermined while data is being set in this RAM, and also during power-on. RAM ON/OFF (GAM_ON) Select signal (GAM_SEL) Input 10 RAM 10 bits x 1024 words 10 Selector 10 Output - 34 - CXD3511AQ (m) Color shading correction This block corrects color shading by adding a correction signal to the video signal. Correction points are set at fixed intervals in the horizontal, vertical and gradual directions of the video signal. The correction data for these correction points is written in the RAM, and a correction curve is created by reading this data and performing interpolation operations. The settings are as follows. CSC_ON: 1 = Color shading correction processing ON, 0 = Processing OFF CSC_R (G, B)_RGT: 1 = Reflects the TG block RGT setting, 0 = Reflects the inverse of the TG block RGT setting CSC_DWN: 1 = Reflects the TG block DWN setting, 0 = Reflects the inverse of the TG block DWN setting CSC_HP: Sets the horizontal correction start position CSC_VP: Sets the vertical correction start position CSC_HNUM: Sets the number of horizontal correction points CSC_VNUM: Sets the number of vertical correction points CSC_HINT: Sets the horizontal correction interval CSC_VINT: Sets the vertical correction interval CSC_HOS: Sets the expansion of the horizontal correction area CSC_VOS: Sets the expansion of the vertical correction area CSC_GNUM: Sets the gradual correction points CSC_R (G, B) GP1 to 8: Sets the gradual correction points CSC_R (G, B) GD1 to 8: Sets the expansion of the correction data CSC_XH_ON: 1 = Cross hatch insertion ON, 0 = OFF CSC_XH_DAT: Sets the cross hatch display level : Set independently for R, G and B, Others: Settings shared by R, G and B The color shading correction data of the desired gradual level up to 8 screens (max.) can be set in RAM. The RAM size is 8 bits x 4096 words, so up to 4096 correction points can be set. The correction data is set as 8-bit data with code. Correction data can be set in the range of -128 to +127 graduation. The example shown on page 37 is for a 1024-dot x 768-line XGA video signal divided into 9 points at 128-dot intervals in the horizontal direction and 7 points at 128-line intervals in the vertical direction. The relationship between the correction point coordinates (m, n) and the RAM address is obtained as follows. RAM address = (m - 1) + (n - 1) x (Number of horizontal correction points) For the example in the figure below, this is as follows. (9 - 1) + (7 - 1) x 9 = 62 Thus, the correction data must be set in the RAM from address 0 to address 62. - 35 - CXD3511AQ If correction is to be performed in the gradual direction as well, the RAM address is found based on the relationship between the coordinates (m, n) of the correction points and the number of gradual correction points using the formula below: RAM address = (m - 1) + (n - 1) x (number of horizontal correction points) + (number of horizontal correction points) x (number of vertical correction points) x (number of gradual correction points - 1) If the number of gradual correction points is eight, it is necessary to set correction data into RAM from Address 0 to Address 503 as calculated below: (9 - 1) + (7 - 1) x 9 + 9 x 7 x 7 = 503 Correction data in the gradual direction for the screen 2 and subsequent planes is set in order from Address 63. This IC supports up/down and/or right/left inversion of the LCD panel by controlling the direction in which correction data that has been set into RAM is read. Up/down and/or right/left inversion are set from DWN and RGT of the TG block. CSC_DWN and CSC_R (G, B)_RGT control the link with the TG block settings. It is therefore unnecessary to reset correction data. The table below gives an example of setting correction points. Correction gap H UXGA (1600 x 1200) SXGA (1280 x 1024) SXGA+ (1400 x 1050) Full-HD (1920 x 1080) XGA (1024 x 768) 64 80 64 64 64 80 64 80 64 64 V 64 80 64 64 64 80 64 80 64 64 H 25 21 21 20 23 19 30 25 17 16 Number of correction points V 19 16 17 16 18 15 17 15 13 12 G 8 8 8 8 8 8 8 8 8 8 Total 3800 2688 2856 2560 3312 2280 4080 3000 1768 1536 Signal specification Example of Setting Correction Points - 36 - CXD3511AQ This IC has two ways it can handle interpolation in the horizontal and vertical directions: by dividing the screen into a uniform grid and setting data for points at the intersections or by setting data for points in the center of each area. (1) When setting data for intersection points (pixels) on the screen The correction area is set for the entire screen. An interpolation operation uses 4 values nearby intermediate points to perform calculations. The correction start position is set using CSC_HP and CSC_VP Be sure to set . the start position for the effective period of the video signal. HDIN VDIN Correction start position Number of correction points 7 8 9 1 1 2 3 4 5 6 Correction start position 2 3 4 (m, n) Correction interval (128 lines) Number of correction points 5 6 7 Correction interval (128 dots) 1024 dots 768 lines : Correction data that has been set in RAM : Interpolation operation results for the vertical direction : Interpolation operation results for the horizontal direction (2) When setting the correction point to the center of the areas dividing the screen The correction area is set to inside the screen. At this time, be sure to set the correction start position so it lies inside the screen. When the correction point is set to the center of the areas dividing the screen, it is necessary to virtually perform correction outside the correction area for which correction data is set. It is therefore assumed that the same data as at the edge of the correction area applies to outside the interpolation area, and linear interpolation is performed. Use CSC_HOS and CSC_VOS to set correction areas that are to be expanded. HDIN VDIN Correction start position Correction start position : Correction data that has been set in RAM : Data assumed to lie in invalid period : Area to be virtually corrected - 37 - CXD3511AQ The number of correction points to be used by this IC for correction in the gradual direction can be set using CSC_GNUM. The number of correction points can be varied from 1 to 8 and settings are available for each RGB signal. This means that the gradual level for which correction is to be performed can be independently and freely set for each RGB signal using CSC_R (G, B) GP1 to 8. An interpolation operation uses 2 values nearby intermediate points to perform linear interpolation. If the number of correction points is 1, no interpolation operation is performed in the gradual direction. The results of interpolation for one screen are added to the video signal regardless of the gradual level of the video signal being input. Correction data for one screen is entered into RAM beginning from Address 0. When two or more correction points are used, interpolation in the gradual direction is performed according to the gradual level of the video signal being input. At this time, set data into RAM for the number of screens equal to "the number of correction points", beginning from Address 0. In the example shown in the figure below, correction data is assigned when there are 5 correction points. In addition to the 5 correction points, data for Screen 1 (Correction Point 1) is assigned to 3FFh. Data for the Screen 5 (Correction Point 5) is assigned to 000h. 3FFh Data for Screen 1 (Correction Point 1) Screen 1 (Correction Point 1) 300h Screen 2 (Correction Point 2) 200h Screen 3 (Correction Point 3) Screen 4 (Correction Point 4) Screen 5 (Correction Point 5) 100h 000h Data for Screen 5 (Correction Point 5) : Correction data that has been set in RAM : Interpolation operation results for the gradual direction Example of Settings for Five Correction Points Furthermore, with this IC, correction data can be extended from 8 bits with code to 9 bits with code. This setting is made using CSC_R (G, B) GD1 to 8. This setting can be made separately for each correction point in the gradual direction as well as independently for each RGB signal. - 38 - CXD3511AQ (n) Selectable delay line block This block supports signal shifting in 1-dot units, performs signal port switching linked with right/left inversion and signal processing that supports dot/line inversion. This block is comprised of five selectors: dot shift selector, right/left inversion selector, dot/line selector, up/ down inversion pre-selector, and up/down inversion post-selector. The delay line size is 1200 words. The data paths for this block are shown in the figure below. Port switching during right/left inversion depends on the Cond1 value, and port switching during up/down inversion (when dot/line inversion support is ON) depends on the Cond2 value. Cond1 = (RGT_SEL_ON) NAND [(RGT) Ex-OR (DLY_R (G, B)_RGT)] Cond2 = (DWN) Ex-NOR (DLY_DWN) Note) RGT and DWN are TG block settings. Input port 1 Dot shift selector Right/left inversion selector Cond1 Dot/line selector Up/down inversion pre-selector Cond2 Delay line Up/down inversion post-selector Cond2 Output port 1 HP[0] Input port 2 DLY_ON Output port 2 Solid lines: 1 Dotted lines: 0 - 39 - CXD3511AQ (1) 1-dot shift When HP[0] = 0, the output data is delayed by one dot compared to when HP[0] = 1. clk port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 port2 out 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 (2) Right/left inversion When Cond1 = 0, signal port switching is performed for the output data. clk port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 IN2 port2 out 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 IN1 - 40 - CXD3511AQ (3) Dot/line inversion support When DLY_ON = 1, signal processing that supports dot/line inverted drive is performed. The output data is output as shown in the figures below according to the Cond1 and Cond2 values. D and the dotted lines in the figures indicate that the signal is delayed by 1H. Cond1 1 Cond2 1 port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 clk port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16 D1 port2 out 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 IN2 Cond1 0 Cond2 1 clk port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17 D2 port2 out 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 IN1 Cond1 1 Cond2 0 clk port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 IN1 port2 out 0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17 D2 Cond1 0 Cond2 0 clk port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18 port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19 port1 out 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 IN2 port2 out 0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16 D1 - 41 - CXD3511AQ (o) Mute 2 block This block performs mute processing by replacing the video signal with data of the desired level. The settings are as follows. MUTE2_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B) R, G, B_MUTE2: RGB mute data (Set independently for R, G and B) Select data (MUTE2_ON) Input Coefficient (R, G, B_MUTE2) 10 10 Selector 10 Output (p) Limiter block This block performs limiter processing so that the output signal does not exceed a certain range. The settings are as follows. L_LIM_DAT: Low side limiter level When input data L_LIM_DAT, the output is clipped to L_LIM_DAT. H_LIM_DAT: High side limiter level When H_LIM_DAT input data, the output is clipped to H_LIM_DAT. (Both settings shared by R, G and B) Set data so that the relationship L_LIM_DAT < H_LIM_DAT is constantly maintained. When both coefficient values are 000h, limiter processing is not performed. Input Coefficient (H_LIM_DAT) Coefficient (L_LIM_DAT) 10 10 10 Limiter 10 Output (q) Post gain block This block performs calculation processing independently for ports 1 and 2. The settings are as follows. Coefficient: 8 bits Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps (Set independently for R, G and B ports 1 and 2) Calculation is performed using the 10-bit input and an 8-bit coefficient, and the upper 12 bits c[17:6] of the operation results are output. Next, the c[6] value is checked and rounding is performed to 11 bits. The MSB of the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output. Coefficient 8 b[7:0] Input 10 a[9:0] 12 c[17:6] Rounding and clipping 10 axb Output - 42 - CXD3511AQ (r) Post bright block This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as follows. Coefficient: 7 bits with code, MSB = code bit Bright setting: -64 to +63 graduation, variable with an accuracy of 1 bit (Set independently for R, G and B ports 1 and 2) Calculation is performed using the 10-bit input and a 7-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[6] = 0, and subtraction when b[6] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Coefficient 7 b[6:0] Input 10 a[9:0] Addition/subtraction and clipping 10 Output (s) Ghost cancel This block uses signal processing to correct ghosting generated internally within the LCD panel. GC_ON: 1 = Ghost cancel processing ON; 0 = OFF (Settings shared by R, G and B) GC_MODE: 1 = 24-dot period processing ON; 0 = 12-dot period processing (Settings shared by R, G and B) R (G, B)_GC_LIM_DAT: Threshould value setting (set independently for R, G and B) R (G, B)_GC_ATT: 8-bit gain data (Set independently for R, G and B) The difference between the video signal prior to 12 or 24 dots and the video signal of dots for which processing is to be performed is found. Attenuation is performed based on this difference and added to the video signal to correct ghosting. In addition, settings can be made so that a limiter is used to ensure processing is performed only when the difference in the video signals is of a set level or higher. Processing Coefficient Coefficient ON/OFF Level selection Input 10 Shift Register 12 levels or 24 levels Arithmetic unit Limiter Attenuator + - Clip processing Output - 43 - CXD3511AQ (t) Cycle offset block This block performs addition and subtraction processing independently for ports 1 and 2. Arithmetic coefficients are selected sequentially using the counter output value as the select signal. Therefore, a cyclic offset relative to the video signal can be attached. The settings are as follows. OFFSET_ON: 1 = Offset processing ON, 0 = OFF (Setting shared by R, G and B) OFFSET_MODE: 0h = 6-dot period, 1h = 12-dot period, 2h = 24-dot period (Setting shared by R, G and B) R, G, B_OFFSET1 to R, G, B_OFFSET24: 5-bit offset data with code -16 to +15 graduation, variable with an accuracy of 1 bit (Set independently for R, G and B) The coefficients selected according to the counter operating period are as shown in the table below. In all cases, the coefficients are assigned in ascending order from the smallest number. The coefficient MSB is the code bit. Addition is performed when MSB = 0, and subtraction when MSB = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed. Coefficient number output from selector Period 6 dots 12 dots 24 dots Port 1 side 1, 3, 5 1, 3, 5, 7, 9, 11 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23 Port 2 side 2, 4, 6 2, 4, 6, 8, 10, 12 1, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 The counter reset timing is delayed by 8 dot clocks from the front edge of the HDIN input. HDIN input (negative polarity) Dot clock 1/2 frequency-divided clock R1, G1, B1OUT R2, G2, B2OUT 8 clocks 1 2 3 4 5 6 7 8 9 10 11 12 Internal HD Internal MCLK OFFSET_MODE 2 5 OFFSET_ON Addition/subtraction and clipping 5 Counter 4 Selector 5 x 24 Coefficient (R, G, B_OFFSET1 to R, G, B_OFFSET24) Input (port 1) 10 10 Output (port 1) Input (port 2) 10 Addition/subtraction and clipping 10 Output (port 2) - 44 - CXD3511AQ 4. Timing Generator (TG) Block This block generates the timing pulses required to drive Sony LCD panels. Of the output pulses, the required pulses differ according to the LCD panel type, so be sure to also check the specifications of the panel used. The output timing pulses are all set by the parallel I/F. For a detailed description, see the description of the parallel I/F TG block. The TG block diagram is shown below. HDIN HSYNC Detect PLL Counter HRS HP Counter HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X, ENBR, ENBL, DENB, PCG, PRG, SHST, HD2 CLP, HD1 H Pulse 1 Generator H Pulse 2 Generator INT_VD VDIN VSYNC Detect INT_HD VP Counter V Pulse Generator VSTR, VSTL, VCKR, VCKL, FRP, XFRP, BLK CTRL Parallel I/F Control Register RGT, DWN XRGT, PO1, 2, 3, 4, 5 Timing Generator Block Diagram - 45 - CXD3511AQ 5. Parallel I/F Block Register data settings in this IC are performed by parallel data. As shown in the Timing Chart below, the parallel I/F comprises a total 12-bit wide bus consisting of control signal PCTL (Pin 12), clock signal PCLK (Pin 13) and 10-bit wide data signal PDAT[9:0] (Pins 14 to 17, 20 to 24 and 26). The data signal is input in the order of main address, sub address and data. When setting data in this IC, divide the data into 19 blocks as shown in the table on the next page. Next, the sub address specifies the initial address of the data to be written in the block designated by the main address. The data is set sequentially from the data at the address designated by the sub address. The address of each data set thereafter is automatically incremented by +1 from the address designated by the sub address, so further address setting is unnecessary. This makes it possible to set only the necessary data from the desired address of the desired block. (1) Timing chart PCTL (Pin 12) PCTL (Pin 13) PDAT[9:0] (Pins 14 to 17, 20 to 24 and 26) Main Sub Address Address Data - 46 - CXD3511AQ (2) Main address table This IC has the RAM size of color shading correction block is 4096 words. One address is divided into four main addresses and mapped. Main address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h TG DSD1 DSD2 Red Gamma Green Gamma Blue Gamma Red CSC (000h to 3FFh) Red CSC (400h to 7FFh) Red CSC (800h to BFFh) Red CSC (C00h to FFFh) Green CSC (000h to 3FFh) Green CSC (400h to 7FFh) Green CSC (800h to BFFh) Green CSC (C00h to FFFh) Blue CSC (000h to 3FFh) Blue CSC (400h to 7FFh) Blue CSC (800h to BFFh) Blue CSC (C00h to FFFh) Pattern Generator Set block - 47 - 5-1. TG Block (Main Address: 000h) The TG block data format is as follows. Data Initial value PDAT7 HR DWN PO2 BLKPOL HSTM FRVC1LNK HSTPOL HSTFIX -- VFRRN[10:2] PLLP[10:1] -- -- HP[9:0] VP[9:0] CLPU[10:1] CLPD[10:1] PRGU[10:1] PRGD[10:1] HD1U[10:1] HD1D[10:1] FRPP[10:1] SHSTU[10:1] SHSTD[10:1] DENU[10:1] DEND[10:1] -- -- SHP[5:0] HSTPC[7:0] -- -- HSTPF[5:0] PSTPC[7:0] -- -- -- -- HP[11:10] -- -- RGVLNK HCKFIX VSTFIX VCKFIX HCKPOL VSTPOL VCKPOL PO5 PO4 PO3 VPOL DCKFINV -- -- DCKFIX DCKPOL RGT PO1 BLKON PSTM SLXBLK PLLP[11] PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 000h 1FFh 3FFh 000h 3FFh 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h Sub address PDAT9 PDAT8 000h POLDET CLKPOL 001h -- HPOL 002h FRPM[1:0] 003h -- -- 004h 005h 006h -- -- 007h 008h - 48 - 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h -- -- 015h -- -- 016h -- -- CXD3511AQ 017h -- -- Data Initial value PDAT7 -- -- PSTPF[5:0] HCKC[5:0] DCK1F[5:0] DCK1W[5:0] DCK2F[5:0] DCK2W[5:0] PCGU[10:1] PDGD[10:1] ENB1U[10:1] ENB1D[10:1] ENB2U[10:1] ENB2D[10:1] VCK1P[10:1] VCK2P[10:1] VST1P[11:2] VST2P[11:2] HD2U[10:1] HD2D[10:1] BLKU[10:1] BLKD[10:1] HD1OE HCK1OE HCK2OE HD2OE CLPOE DCKOE PRGOE DCKXOE SHSTOE V1OE DENOE V2OE FRPOE PCGOE XFRPOE BLKOE -- -- -- -- -- -- -- -- -- -- 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 Sub address PDAT9 PDAT8 018h -- -- 019h -- -- 01Ah -- -- 01Bh -- -- 01Ch -- -- 01Dh -- -- 01Eh 01Fh 020h 021h 022h 023h - 49 - 024h 025h 026h 027h 028h 029h 02Ah 02Bh 02Ch -- CLKOUT 02Dh HSTOE PSTOE --: Don't care CXD3511AQ CXD3511AQ The detailed setting contents are described below. (a) Clock settings (1) CLKPOL (sub address: 000h) This sets the internal clock polarity. Setting value: 1 = Inverted, 0 = Not inverted The clock flow from the clock input pins to the PLL block is shown below. CLKP CLKN To PLL Block CLKC 1/2 CLKSEL1 CLKSEL2 CLKPOL (2) CLKOUT (sub address: 02Ch) This sets the Pin 47 clock output limit. Setting value: 1 = Inverted clock is output, 0 = Low is output (b) SYNC polarity settings (1) POLDET (sub address: 000h) This sets the sync polarity auto discrimination function ON/OFF. Setting value: 1 = Auto discrimination function ON, 0 = Auto discrimination function OFF When POLDET = 1, the HPOL and VPOL settings below are invalid. When using this function, the HDIN sync portion must be 1/2 or less of 1H, and the VDIN sync portion must come before the rise position of the VSTL/ R pulse. HDIN (Negative) N/2 or less N VDIN (Negative) Must come before VSTL/R VSTL/R (2) HPOL and VPOL (sub address: 001h) These set the sync signal polarity when POLDET = 0. Setting value: 1 = Positive polarity, 0 = Negative polarity The internal operation of this IC is with the input sync signal fixed to positive polarity. Therefore, these HPOL and VPOL must be set in accordance with the polarity of the sync signal input from HDIN and VDIN. Set HPOL and VPOL to "1" when the input sync signal is positive polarity, or to "0" when negative polarity. - 50 - CXD3511AQ (c) Dots per 1H and lines per 1F settings (1) HR (sub address: 000h) This sets the PLL counter reset ON/OFF. Setting value: 1 = Reset enabled, 0 = Reset disabled When HR = 0, the internal frequency divider is used, and the HD1 pulse output should be used as the return pulse. The number of dot clocks per 1H is set by PLLP[11:1] below. (2) PLLP[11:1] (sub addresses: 004h and 005h) This sets the internal PLL counter reset period in 11 bits. Setting is possible in 2-dot units. When the number of dot clocks per 1H is N, set the "(N - 2)/2" value. When HR = 0, free-running occurs at the above N. When HR = 1, if the next HDIN is not input before the internal PLL counter counts up to 2047, free-running mode is established and free-running occurs at N. When HDIN is input, free-running is canceled and normal operation is established. (3) VFRRN[10:2] (sub address: 004h) This sets the number of lines in 9 bits during vertical free running. Setting is possible in 4-line units. To have operation run freely at M lines, set the "(M - 4)/4" value. If the next VDIN is not input before the internal vertical line counter counts up to 2047, free-running mode is established. When VDIN is input, free-running is canceled and normal operation is established. (d) Scan direction settings RGT and DWN (sub address: 000h) These settings switch the scan directions of the LCD panel. Setting value: 1 = Forward scan, 0 = Reverse scan When CTRL (Pin 148) is low, RGT (Pin 136) and DWN (Pin 147) function as output pins, and the data set in the respective registers is reflected. When CTRL is high, this setting is ignored, RGT and DWN function as input pins, and are reflected to internal operation. (e) Register parallel output settings PO1, PO2, PO3, PO4 and PO5 (sub address: 000h) These set the register setting parallel output. Setting value: 1 = High is output, 0 = Low is output The set data is reflected to the output pins PO1 (Pin 154), PO2 (Pin 153), PO3 (Pin 152), PO4 (Pin 164) and PO5 (Pin 166) of the same name. - 51 - CXD3511AQ (f) Horizontal display position and horizontal direction pulse settings (1) HP[11:0] (sub addresses: 006h and 007h) HP[11:1] sets the horizontal pulse position for the LCD panel in 11 bits. The position can be set in 2-dot units using the internal pulse INT_HD generated from the front edge of HDIN as the reference. The HP setting range is from "0 to (N - 2)". If the HP value is set to the number of frequency divisions N or higher, the HP setting is ignored and "(N - 2)" is used as the setting value. The HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X, ENBL, ENBR, VSTL, VSTR, VCKL, VCKR, FRP , XFRP PCG, PRG, BLK and HD2 horizontal timing pulses are linked according to the HP setting. , The internal reference pulse INT_HD rises at the 5th clock from the front edge of the HDIN input, and all the pulses are synchronized using this as the reference. Increasing HP shifts the output positions of the linked pulses toward the rear of the time series. The example below shows the shortest output position from HDIN when HP is set to 000h. (Note that the output position changes according to the settings in (2) below.) HP[0] can shift the video in 1-dot units. See 3. Description of DSD Block Signal Processing Functions, (n) Selectable delay line block, (1) 1-dot shift for a detailed description. Internal CLK HDIN INT_HD HD1 HD2 (2) CLPU[10:1], CLPD[10:1], PRGU[10:1], PRGD[10:1], HD1U[10:1], HD1D[10:1], SHSTU[10:1], SHSTD[10:1], DENU[10:1], DEND[10:1], PCGU[10:1], PCGD[10:1], ENB1U[10:1], ENB1D[10:1], ENB2U[10:1], ENB2D[10:1], HD2U[10:1], HD2D[10:1] (sub addresses: 009h to 013h, 01Eh to 023h and 028h to 029h) These set the horizontal timing pulse output positions in 10 bits. The respective rise and fall positions can be set in 2-dot units. Settings ending in "U" set the rise position, and settings ending in "D" set the fall position. Horizontal pulses are divided into the following two types. (A) CLP and HD1 Pulses synchronized to the PLL counter Set the "(rise position/fall position - 10)/2" value. (B) PRG, SHST, DEN, PCG, ENBL, ENBR and HD2 Pulses synchronized to the HP counter Set the "(rise position/fall position - HP setting value - 16)/2" value. An outline of each type is shown below. When U and D are set to the same value, "1" is output. HDIN 0 PLL counter 0 HP counter HP[11:1] (A) U U D D 0 0 (B) (3) HD1OE, HD2OE, CLPOE, PRGOE, SHSTOE, DENOE and PCGOE (sub addresses: 02Ch and 02Dh) These set the output limit of HD1, HD2, CLP PRG, SHST, DEN and PCG pulses, respectively. , Setting value: 1 = Pulse is output, 0 = Output is fixed to "0" - 52 - CXD3511AQ (g) Vertical display position setting VP[9:0] (sub address: 008h) This sets the vertical display start position in 10 bits. The position can be set in 1-line units using the front edge of VDIN as the reference. The VSTL/VSTR, VCKL/VCKR, FRP and XFRP pulse phases change by linking with this setting. Minimum adjustment width: 1H Tvp VDIN HDIN VSTL VCKL Tvp minimum and maximum setting values Min. VP[9:0] Tvp 000h 6H Max. 3FFh 1029H - 53 - CXD3511AQ (h) HST and PST pulse settings (1) HSTM (sub address: 002h) This sets the pulse width for horizontal display start timing pulse HST. Setting value: 1 = Twice the HCK period width, 0 = HCK period width Set the width according to the LCD panel specifications. (2) PSTM (sub address: 002h) This sets the pulse width for dot sequential precharge start timing pulse PST. Setting value: 1 = Twice the HCK period width, 0 = HCK period width Set the width according to the LCD panel specifications. HSTM, PSTM = 0 HST, PST HST, PST HSTM, PSTM = 1 HCK1 HCK1 (3) HSTFIX and HSTPOL (sub addresses: 001h and 002h) These set the HST and PST pulse output polarities. The polarity changes as follows according to the combination of linked/not linked with control signal RGT. This setting is shared by HST and PST. HSTFIX 0 0 0 0 1 1 1 1 HSTPOL 0 0 1 1 0 0 1 1 RGT 0 1 0 1 0 1 0 1 Output polarity Positive Negative Negative Positive Negative Negative Positive Positive - 54 - CXD3511AQ (4) HSTPC[7:0], HSTPF[5:0], PSTPC[7:0] and PSTPF[5:0] (sub addresses: 015h to 018h) These set the HST and PST pulse phases. Reset is applied when the internal HP counter reaches "0", and the HST and PST pulse phases within 1H can be set at the HCK1 and HCK2 period, respectively, by HSTPC and PSTPC. HSTPF and PSTPF can set the HST and PST pulse phase relative to HCK1 and HCK2 in 1-dot units. Do not set HSTPC and PSTPC to 00h, as the pulses may not be output correctly in this case. The HSTPF and PSTPF values can be set up to "(HCKC x 2 - 2)". If higher values are set, the pulses are not output. Set the "(phase difference from HCK pulse)" value. The figures below show the timings for HSTPC: 04h and HSTPF: 04h, respectively. These timings are the same for the PST pulse. HSYNC 0 HP counter HP[11:0] HCK1 0 HST Setting prohibited HSTPF[5:0] 1 2 3 4 5 6 7 MCLK HCK1 HST HSTPF: 04h (5) HSTOE and PSTOE (sub address: 02Dh) These set the output limit of HST and PST pulses, respectively. Setting value: 1 = Pulse is output, 0 = Output is fixed to "0" - 55 - CXD3511AQ (i) HCK1 and HCK2 pulse settings (1) HCKC[5:0] (sub address: 019h) This sets the HCK1 and HCK2 period (LCD panel sampling period). Settings which result in an odd number for Tckw in the figure below are prohibited, so be sure to set a value that results in an even number. Set the "(Tckw - 1)" value according to the LCD panel specifications. When this setting is changed, the HST and PST pulse phases also change, so first set HCKC to the correct value and then make the HST and PST settings. Example setting values are shown in the table below. LCD panel SVGA, WXGA XGA, SXGA UXGA Tckw 6 clk 12 clk 24 clk HCKC setting 05h 0Bh 17h MCLK HCK1 1 clk Tckw (2) HCKFIX and HCKPOL (sub addresses: 001h and 002h) These set the HCK pulse output polarity. The polarity relative to the HST pulse changes as follows according to the combination of linked/not linked with control signal RGT. HCKFIX 0 0 0 0 1 1 1 1 Positive HST HST HCKPOL 0 0 1 1 0 0 1 1 RGT 0 1 0 1 0 1 0 1 Output polarity Positive Negative Negative Positive Negative Negative Positive Positive Negative HCK1 HCK1 HSTPF[7:0] = 00h (3) HCK1OE and HCK2OE (sub address: 02Dh) These set the output limit of HCK1 and HCK2 pulses, respectively. Setting value: 1 = Pulse is output, 0 = Output is fixed to "0" - 56 - CXD3511AQ (j) DCK1, DCK1X, DCK2 and DCK2X pulse settings (1) DCK1F[5:0], DCK1W[5:0], DCK2F[5:0] and DCK2W[5:0] (sub addresses: 01Ah to 01Dh) These set the DCK1, DCK1X, DCK2 and DCK2X pulse phases and widths. DCK1F sets the DCK1 and DCK1X pulse phases relative to HCK1 and HCK2 in 1-dot units, and DCK2F sets the DCK2 and DCK2X pulse phases relative to HCK1 and HCK2 in 1-dot units. Set the "Tdck1 (2) f" value. The DCKFINV, DCKFIX and RGT settings differ according to whether the phase is synchronized with the rising edge of HCK1 or HCK2. The DCK1 and DCK1X pulse width and the DCK2 and DCK2X pulse width can be set in 2-dot units by DCK1W and DCK2W, respectively. Set the "(Tdck1 (2) W - 2)/2" value. HCK1 HCK2 Tdck1f DCK1 DCK1X Tdck2f DCK2 DCK2X Tdck2w Tdck1w (2) DCKPOL (sub address: 001h) This setting switches the DCK1 and DCK1X, DCK2 and DCK2X output polarities. Switching this setting, inverts the polarities each pair of DCK1 and DCK1X, DCK2 and DCK2X at once. - 57 - CXD3511AQ (3) DCKFINV and DCKFIX (sub address: 002h) This setting switches the DCK1 and DCK1X, DCK2 and DCK2X output phases relative to HCK1 and HCK2. The phase changes as follows according to the combination of linked/not linked with right/left inversion control signal RGT. DCKFIX 0 0 0 0 1 1 1 1 DCKFINV 0 0 1 1 0 0 1 1 RGT 0 1 0 1 0 1 0 1 Output phase A B B A B B A A A HCK1 HCK2 HCK1 HCK2 B DCK1 DCK2 DCK1 DCK2 (4) DCKOE (sub address: 02Dh) This sets the output limit of DCK1 and DCK2 pulses. Setting value: 1 = DCK1 and DCK2 pulses are output, 0 = Output is fixed to "0" (5) DCKXOE (sub address: 02Dh) This sets the output limit of DCK1X and DCK2X pulses. Setting value: 1 = DCK1X and DCK2X pulses are output, 0 = Output is fixed to "0" - 58 - CXD3511AQ (k) LCD panel sample-and-hold position setting SHP[5:0] (sub address: 014h) This sets the horizontal transfer start pulse and clock pulse phases relative to the video signal to the LCD panel. The phase can be set in 64 positions with 6 bits. Incrementing SHP by +1 shifts the HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2 and DCK2X pulses forward by 1 dot (half the internal clock period). The LCD panel sample-and-hold position can be set by shifting the above pulse phases forward or backward relative to the video signal. At this time, the phases between the HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2 and DCK2X pulses do not change. The figure below shows an example of HCK1 during 12-dot simultaneous sampling. This setting eliminates the need to set the sample-and-hold position with a Sony sample-and-hold driver IC, and makes it possible to adjust the phases of the video signal to the LCD panel and the horizontal transfer clock without changing the position of the video signal on the screen. Video signal to LCD panel HCK1 SHP increased Internal CLK SHP decreased - 59 - CXD3511AQ (l) VST and VCK pulse settings (1) VST1P[11:2] and VST2P[11:2] (sub addresses: 026h to 027h) These set the VSTL and VSTR pulse rise and fall positions within 1H in 10 bits. The positions can be set in 4-dot units using the internal HP counter "0" position as the reference. Set the "(Tvstp - 4)/4" value. See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VST1P or VST2P settings is reflected to VSTL or VSTR. HDIN HP counter 0 VST VCK Tvckp Tvstp (2) VCK1P[10:1] and VCK2P[10:1] (sub addresses: 024h to 025h) These set the VCKL and VCKR, FRP and XFRP inversion positions within 1H in 10 bits. The positions can be set in 2-dot units using the internal HP counter "0" position as the reference. Set the "(Tvckp - 2)/2" value. See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VCK1P VCK2P or FRPP , settings is reflected to VCKL or VCKR. (3) VSTFIX and VCKFIX (sub address: 002h), VSTPOL and VCKPOL (sub address: 001h) These set the VST and VCK pulse output polarities. The VSTL and VSTR pulse polarities and the VCKL and VCKR pulse polarities relative to the VSTL and VSTR pulses change as follows according to the combination of linked/not linked with control signal DWN. FIX 0 0 0 0 1 1 1 1 POL 0 0 1 1 0 0 1 1 DWN 0 1 0 1 0 1 0 1 Output polarity Positive Negative Negative Positive Negative Negative Positive Positive : VST or VCK (4) V1OE (sub address: 02Dh) This sets the output limit of VSTL, VCKL and ENBL pulses. Setting value: 1 = VSTL, VCKL and ENBL pulses are output, 0 = Output is fixed to "0" (5) V2OE (sub address: 02Dh) This sets the output limit of VSTR, VCKR and ENBR pulses. Setting value: 1 = VSTR, VCKR and ENBR pulses are output, 0 = Output is fixed to "0" - 60 - CXD3511AQ (m) FRP and XFRP pulse settings (1) FRPM[1:0] (sub address: 002h) This sets the period for switching the LCD AC conversion signal FRP pulse. 1F/1H, 2F/1H, 1F and 2F inversion can be set as shown in the figure below. Normally use FRP1, 0: 11. 1H FRP1, 0: 11 (1F/1H inversion) FRP1, 0: 01 (2F/1H inversion) FRP1, 0: 10 (1F inversion) FRP1, 0: 00 (2F inversion) 1F (2) FRPP[10:1] (sub address: 00Fh) This sets the FRP and XFRP inversion positions within 1H in 10 bits. The positions can be set in 2-dot units using the internal HP counter "0" position as the reference. Set the "(FRP inversion position - HP counter "0" position - 2)/2" value. XFRP is output as the polarity inverted FRP pulse. (3) FRPOE and XFRPOE (sub address: 02Ch) These set the output limit of FRP and XFRP pulses, respectively. Setting value: 1 = Pulse is output, 0 = Output is fixed to "0" - 61 - CXD3511AQ (n) VCK and FRP transition point shared setting and V block pulse right/left inversion link setting FRVC1LNK and RGVLNK (sub address: 003h) These set the VCKL and VCKR transition points Setting value: 1 = FRP and VCK transition points are shared, 0 = FRP and VCK transition points are independent When FRVC1LNK = 1, the VCK inversion timing is forcibly synchronized with the FRP inversion timing. At this time, which of VCKL or VCKR is linked with the FRP transition point is as follows. When FRVC1LNK = 0, the VCKL and VCKR transition points are determined by VCK1P[10:1] or VCK2P[10:1] according to the RGT setting. When RGVLNK = 1, the V block pulses, VSTL, VCKL and ENBL are switched with VSTR, VCKR and ENBR, respectively, linked with right/left inversion control signal RGT. When RGVLNK = 0, the V block pulses are fixed regardless of the RGT setting. See the following page for a detailed description. FRVC1LNK 0 0 0 0 1 1 1 1 RGVLNK 0 0 1 1 0 0 1 1 RGT 0 1 0 1 0 1 0 1 Output waveform A A B A C C D C VCKL VCK1P A VCKR FRP VCK2P FRPP VCKL VCK2P B VCKR VCK1P FRP FRPP VCKL C VCKR FRP VCK2P FRPP VCKL VCK2P D VCKR FRP FRPP - 62 - CXD3511AQ (o) V scanner pulse scan direction link setting RGVLNK (sub address: 003h) This sets whether to link the V block pulses, VSTL, VSTR, VCKL, VCKR, ENBL and ENBR with the right/left inversion control signal RGT. Setting value: 1 = Linked with RGT, 0 = Independent of RGT When RGVLNK = 1, rise and fall positions of VSTL and VSTR, ENBL and ENBR pulses and inversion position of VCKL and VCKR pulses are switched respectively by linking with RGT. When RGVLNK = 0, VSTL, VCKL and ENBL are set by VST1P VCK1P, ENB1U and ENB1D, respectively, and VSTR, VCKR and ENBR are set , by VST2P VCK2P ENB2U and ENB2D, respectively, independent of the RGT setting. , , RGVLNK 0 0 1 1 RGT 0 1 0 1 Output waveform A A B A VSTL VST1P VSTR VST2P VCKL A VCKR VCK2P ENBL ENBR ENB1D ENB1U ENB2D ENB2U VCK1P VSTL VST2P VSTR VST1P VCKL B VCKR VCK1P ENBL ENBR ENB1D ENB2D ENB1U ENB2U VCK2P - 63 - CXD3511AQ (p) BLK pulse settings (1) BLKON (sub address: 001h) This sets the black frame write pulse BLK ON/OFF. Setting value: 1 = Pulse is output, 0 = DC is output When BLKON = 1, BLK is output as a single pulse in 1V. (2) BLKPOL (sub address: 001h) This sets the black frame write pulse BLK polarity. Setting value: 1 = Positive polarity, 0 = Negative polarity Set BLKPOL = 1 for a Sony SVGA panel, and BLKPOL = 0 for an XGA panel. VST BLKON: 1, BLKPOL: 1 BLKON: 0, BLKPOL: 1 BLKON: 1, BLKPOL: 0 BLKON: 0, BLKPOL: 0 BLK BLK BLK BLK (3) SLXBLK (sub address: 003h) This sets the precharge waveform top/bottom black frame display mode. Setting value: 1 = XGA type, 0 = Other than XGA type Set SLXBLK = 1 only when using top/bottom black frame display mode on a Sony XGA type LCD panel. Set SLXBLK = 0 in all other cases. VST VCK SLXBLK: 0 BLK PRG PCG VST VCK SLXBLK: 1 BLK PRG PCG - 64 - CXD3511AQ (4) BLKU[10:1] and BLKD[10:1] (sub addresses: 02Ah to 02Bh) These set the BLK pulse rise and fall positions within 1H in 10 bits. The positions can be set in 2-dot units using the internal HP counter "0" position as the reference. Set the "(BLK rise/fall position - HP counter "0" position - 2)/2" value. (5) BLKOE (sub address: 02Dh) This is the output limit of BLK pulse. Setting value: 1 = Pulse is output, 0 = Output is fixed to "0" - 65 - 5-2. DSD1 Block (Main Address: 001h) The DSD1 block data format is as follows. Data Initial value PDAT7 PDAT0 000h R1_PRE_BRT[4:0] R2_PRE_GAIN[7:0] -- -- G1_PRE_GAIN[7:0] -- -- G2_PRE_GAIN[7:0] -- -- B1_PRE_GAIN[7:0] -- -- B2_PRE_GAIN[7:0] MUTE1_ON GAM_ON USER_GAIN[7:0] USER_BRT[9:0] R_SUB_GAIN[7:0] R_SUB_BRT[9:0] G_SUB_GAIN[7:0] G_SUB_BRT[9:0] B_SUB_GAIN[7:0] B_SUB_BRT[9:0] R_MUTE1[9:0] G_MUTE1[9:0] B_MUTE1[9:0] R_OSD_DAT1[9:0] R_OSD_DAT2[9:0] GAM_SEL B2_PRE_BRT[4:0] -- B1_PRE_BRT[4:0] -- G2_PRE_BRT[4:0] -- G1_PRE_BRT[4:0] -- R2_PRE_BRT[4:0] 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h R1_PRE_GAIN[7:0] -- -- -- PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 Sub address PDAT9 PDAT8 000h -- R_DAT_SW 001h -- -- 002h -- -- 003h -- -- 004h -- G_DAT_SW 005h -- -- 006h -- -- 007h -- -- 008h -- B_DAT_SW 009h -- -- - 66 - 00Ah -- -- 00Bh -- -- 00Ch -- USER_BRT[10] 00Dh 00Eh -- R_SUB_BRT[10] 00Fh 010h -- G_SUB_BRT[10] 011h 012h -- B_SUB_BRT[10] 013h 014h 015h 016h 017h CXD3511AQ 018h Sub address PDAT7 R_OSD_DAT3[9:0] 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h R2_POST_BRT[6:0] G1_POST_GAIN[7:0] -- G1_POST_BRT[6:0] G2_POST_GAIN[7:0] -- G2_POST_BRT[6:0] B1_POST_GAIN[7:0] -- B1_POST_BRT[6:0] B2_POST_GAIN[7:0] -- B2_POST_BRT[6:0] 000h 000h 000h 000h 000h 000h 000h 000h 000h R_OSD_DAT4[9:0] G_OSD_DAT1[9:0] G_OSD_DAT2[9:0] G_OSD_DAT3[9:0] G_OSD_DAT4[9:0] B_OSD_DAT1[9:0] B_OSD_DAT2[9:0] B_OSD_DAT3[9:0] B_OSD_DAT4[9:0] R_MUTE2[9:0] G_MUTE2[9:0] B_MUTE2[9:0] L_LIM_DAT[9:0] H_LIM_DAT[9:0] R1_POST_GAIN[7:0] -- R1_POST_BRT[6:0] R2_POST_GAIN[7:0] -- PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 Initial value Data PDAT9 PDAT8 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 021h 022h 023h 024h 025h - 67 - 026h 027h 028h -- MUTE2_ON 029h -- -- 02Ah -- -- 02Bh -- -- 02Ch -- -- 02Dh -- -- 02Eh -- -- 02Fh -- -- 030h -- -- 031h -- -- 032h -- -- CXD3511AQ 033h -- -- --: Don't care CXD3511AQ The detailed setting contents are described below. (a) R_DAT_SW, G_DAT_SW and B_DAT_SW (sub addresses: 000h, 004h and 008h) These select the data path switch block data path. Setting value: 1 = Data path is switched, 0 = Data path is not switched (b) R1_PRE_GAIN[7:0], R2_PRE_GAIN[7:0], G1_PRE_GAIN[7:0], G2_PRE_GAIN[7:0], B1_PRE_GAIN[7:0] and B2_PRE_GAIN[7:0] (sub addresses: 000h, 002h, 004h, 006h, 008h and 00Ah) These set the pre gain block arithmetic coefficients in 8 bits. (c) R1_PRE_BRT[4:0], R2_PRE_BRT[4:0], G1_PRE_BRT[4:0], G2_PRE_BRT[4:0], B1_PRE_BRT[4:0] and B2_PRE_BRT[4:0] (sub addresses: 001h, 003h, 005h, 007h, 009h and 00Bh) These set the pre bright block arithmetic coefficients in 5 bits with code. (d) USER_GAIN[7:0] (sub address: 00Ch) This sets the user gain block arithmetic coefficients in 8 bits. (e) USER_BRT[10:0] (sub addresses: 00Ch and 00Dh) This sets the user bright block arithmetic coefficients in 11 bits with code. (f) R_SUB_GAIN[7:0], G_SUB_GAIN[7:0] and B_SUB_GAIN[7:0] (sub addresses: 00Eh, 010h and 012h) These set the R, G and B sub gain block arithmetic coefficients in 8 bits. (g) R_SUB_BRT[10:0], G_SUB_BRT[10:0] and B_SUB_BRT[10:0] (sub addresses: 00Eh to 013h) These set the R, G and B sub bright block arithmetic coefficients in 11 bits with code. (h) MUTE1_ON (sub address: 00Bh) This selects mute 1 block processing ON/OFF. Setting value: 1 = Mute processing ON, 0 = OFF (i) R_MUTE1[9:0], G_MUTE1[9:0] and B_MUTE1[9:0] (sub addresses: 014h to 016h) These set the mute 1 block data in 10 bits. - 68 - CXD3511AQ (j) R_OSD_DAT1 to 4[9:0], G_OSD_DAT1 to 4[9:0] and B_OSD_DAT1 to 4[9:0] (sub addresses: 014h to 022h) These set the OSD block decode data in 10 bits. (k) GAM_SEL (sub address: 00Bh) This selects the gamma block data path. Setting value: 1 = Path passing through the RAM, 0 = Path not passing through the RAM (l) GAM_ON (sub address: 00Bh) This sets the gamma block RAM operating mode. Setting value: 1 = Normal operation, 0 = Standby mode Note that in standby mode, data cannot be written to or read from the RAM. Also, previously set data is held even when the RAM is set to standby mode. (m) L_LIM_DAT[9:0] and H_LIM_DAT[9:0] (sub addresses: 026h and 027h) These set the limiter block limit value data in 10 bits. Be sure to maintain the relationship L_LIM_DAT < H_LIM_DAT. Note that when both coefficients are set to 000h, limiter processing is not performed. (n) MUTE2_ON (sub address: 028h) This selects the mute 2 block processing ON/OFF. Setting value: 1 = Mute processing ON, 0 = OFF (o) R_MUTE2[9:0], G_MUTE2[9:0] and B_MUTE2[9:0] (sub addresses: 023h to 025h) These set the mute 2 block data in 10 bits. (p) R1_POST_GAIN[7:0], R2_POST_GAIN[7:0], G1_POST_GAIN[7:0], G2_POST_GAIN[7:0], B1_POST_GAIN[7:0] and B2_POST_GAIN[7:0] (sub addresses: 028h, 02Ah, 02Ch, 02Eh, 030h and 032h) These set the post gain block arithmetic coefficients in 8 bits. (q) R1_POST_BRT[6:0], R2_POST_BRT[6:0], G1_POST_BRT[6:0], G2_POST_BRT[6:0], B1_POST_BRT[6:0] and B2_POST_BRT[6:0] (sub addresses: 029h, 02Bh, 02Dh, 02Fh, 031h and 033h) These set the post bright block arithmetic coefficients in 7 bits with code. - 69 - 5-3. DSD2 Block (Main Address: 002h) The DSD2 block data format is as follows. Data Initial value DATA7 FRM_DAT[9:0] FRM_H1[9:0] FRM_H2[9:0] FRM_V1[9:0] FRM_V2[9:0] -- FRM_V1[10] FRM_H1[11:10] CSC_DWN CSC_HP[9:1] CSC_VP[7:0] -- -- -- -- -- -- -- CSC_RGP1[9:1] CSC_RGP2[9:1] CSC_RGP3[9:1] CSC_RGP4[9:1] CSC_RGP5[9:1] CSC_RGP6[9:1] CSC_RGP7[9:1] CSC_RGP8[9:1] CSC_GGP1[9:1] -- -- -- -- -- CSC_HNUM[5:0] CSC_VNUM[5:0] CSC_HINT[7:2] CSC_VINT[7:2] CSC_HOS[7:2] CSC_VOS[7:2] CSC_B_RGT CSC_GNUM[2:0] FRM_V2[10] CSC_ON FRM_ON FRM_H2[11:10] CSC_G_RGT CSC_R_RGT DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h Sub address DATA9 DATA8 000h 001h 002h 003h 004h 005h -- -- 006h -- CSC_XH 007h -- 008h -- -- - 70 - 009h -- -- 00Ah -- -- 00Bh -- -- 00Ch -- -- 00Dh -- -- 00Eh -- -- 00Fh CSC_RGD1 010h CSC_RGD2 011h CSC_RGD3 012h CSC_RGD4 013h CSC_RGD5 014h CSC_RGD6 015h CSC_RGD7 016h CSC_RGD8 CXD3511AQ 017h CSC_GGD1 Data Initial value DATA7 DATA0 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h R_GC_ATT[7:0] G_GC_ATT[7:0] B_GC_ATT[7:0] OFFSET_MODE[1:0] R_OFFSET2[4:0] R_OFFSET4[4:0] R_OFFSET6[4:0] RGT_SEL_ON DLY_ON DLY_DWN DLY_B_RGT R_OFFSET1[4:0] R_OFFSET3[4:0] R_OFFSET5[4:0] DLY_G_RGT DLY_R_RGT 000h 000h 000h 000h 000h 000h 000h CCS_GGP2[9:1] CCS_GGP3[9:1] CCS_GGP4[9:1] CCS_GGP5[9:1] CCS_GGP6[9:1] CCS_GGP7[9:1] CCS_GGP8[9:1] CSC_BGP1[9:1] CSC_BGP2[9:1] CSC_BGP3[9:1] CSC_BGP4[9:1] CSC_BGP5[9:1] CSC_BGP6[9:1] CSC_BGP7[9:1] CSC_BGP8[9:1] CSC_XH_DAT[9:2] R_GC_LIM_DAT[9:0] G_GC_LIM_DAT[9:0] B_GC_LIM_DAT[9:0] DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 Sub address DATA9 DATA8 018h CSC_GGD2 019h CSC_GGD3 01Ah CSC_GGD4 01Bh CSC_GGD5 01Ch CSC_GGD6 01Dh CSC_GGD7 01Eh CSC_GGD8 01Fh CSC_BGD1 020h CSC_BGD2 021h CSC_BGD3 022h CSC_BGD4 023h CSC_BGD5 - 71 - 024h CSC_BGD6 025h CSC_BGD7 026h CSC_BGD8 027h -- -- 028h 029h 02Ah 02Bh GC_ON GC_MODE 02Ch -- -- 02Dh -- -- 02Eh -- OFFSET_ON 02Fh 030h CXD3511AQ 031h Data Initial value DATA7 DATA0 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h G_OFFSET7[4:0] G_OFFSET9[4:0] G_OFFSET11[4:0] G_OFFSET13[4:0] G_OFFSET15[4:0] G_OFFSET17[4:0] G_OFFSET19[4:0] G_OFFSET21[4:0] G_OFFSET23[4:0] B_OFFSET1[4:0] B_OFFSET3[4:0] B_OFFSET5[4:0] B_OFFSET7[4:0] B_OFFSET9[4:0] B_OFFSET11[4:0] 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h R_OFFSET8[4:0] R_OFFSET7[4:0] R_OFFSET9[4:0] R_OFFSET11[4:0] R_OFFSET13[4:0] R_OFFSET15[4:0] R_OFFSET17[4:0] R_OFFSET19[4:0] R_OFFSET21[4:0] R_OFFSET23[4:0] G_OFFSET1[4:0] G_OFFSET3[4:0] G_OFFSET5[4:0] R_OFFSET10[4:0] R_OFFSET12[4:0] R_OFFSET14[4:0] R_OFFSET16[4:0] R_OFFSET18[4:0] R_OFFSET20[4:0] R_OFFSET22[4:0] R_OFFSET24[4:0] G_OFFSET2[4:0] G_OFFSET4[4:0] G_OFFSET6[4:0] G_OFFSET8[4:0] G_OFFSET10[4:0] G_OFFSET12[4:0] G_OFFSET14[4:0] G_OFFSET16[4:0] G_OFFSET18[4:0] G_OFFSET20[4:0] G_OFFSET22[4:0] G_OFFSET24[4:0] B_OFFSET2[4:0] B_OFFSET4[4:0] B_OFFSET6[4:0] B_OFFSET8[4:0] B_OFFSET10[4:0] B_OFFSET12[4:0] DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 Sub address DATA9 DATA8 032h 033h 034h 035h 036h 037h 038h 039h 03Ah 03Bh 03Ch 03Dh - 72 - 03Eh 03Fh 040h 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah CXD3511AQ 04Bh 04Ch Data Initial value DATA7 DATA0 000h 000h 000h 000h 000h 000h B_OFFSET14[4:0] B_OFFSET16[4:0] B_OFFSET18[4:0] B_OFFSET20[4:0] B_OFFSET22[4:0] B_OFFSET24[4:0] B_OFFSET23[4:0] B_OFFSET21[4:0] B_OFFSET19[4:0] B_OFFSET17[4:0] B_OFFSET15[4:0] B_OFFSET13[4:0] DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 Sub address DATA9 DATA8 04Dh 04Eh 04Fh 050h 051h 052h --: Don't care - 73 - CXD3511AQ CXD3511AQ The detailed setting contents are described below. (a) FRM_ON (sub address: 005h) This sets the processing ON/OFF for the black frame block. Setting value: 1 = Black frame processing ON, 0 = Black frame processing OFF (b) FRM_DAT[9:0] (sub address: 000h) This sets the data for the black frame processing block in 10 bits. (c) FRM_H1[11:0] and FRM_H2[11:0] (sub addresses: 001h, 002h and 005h) These set the horizontal black frame display range for the black frame block in 12 bits. The range can be set in 1-dot units. Set the "display range" value. HDIN FRM_H1 FRM_H2 Black frame display range Black frame display range (d) FRM_V1[10:0] and FRM_V2[10:0] (sub addresses: 003h to 005h) These set the vertical black frame display range for the black frame block in 11 bits. The range can be set in 1-line units. Set the "display range - 2" value. VDIN FRM_V1 FRM_V2 Black frame display range Black frame display range (e) CSC_ON (sub address: 006h) This sets the processing ON/OFF for the color shading correction block. Setting value: 1 = ON, 0 = OFF (f) CSC_R_RGT, CSC_G_RGT and CSC_B_RGT (sub address: 006h) These set the right/left inversion for the color shading correction block. Setting value: 1 = Reflects the TG block RGT setting, 0 = Reflects the inverse of TG block RGT setting (g) CSC_DWN (sub address: 006h) This sets the up/down inversion for the color shading correction block. Setting value: 1 = Reflects the TG block DWN setting, 0 = Reflects the inverse of TG block DWN setting - 74 - CXD3511AQ (h) CSC_HP[9:1] (sub address: 007h) This sets the horizontal correction start position for the color shading correction block in 9 bits. The position can be set in 2-dot units. The setting range is 020h to 1FEh. Set the "correction start position + 1" value. (i) CSC_VP[7:0] (sub address: 008h) This sets the vertical correction start position for the color shading correction block in 8 bits. The position can be set in 1-line units. The setting range is 00h to FEh. Set the "correction start position - 4" value. (j) CSC_HNUM[5:0] and CSC_VNUM[5:0] (sub addresses: 009h and 00Ah) These set the number of horizontal and vertical correction points for the color shading correction block in 6 bits in the range of 2 to 64 points. Set the "number of correction points - 1" value. The size of the RAM for setting the correction data is 4096 words, so set the number of correction points as follows. Number of horizontal correction points x Number of vertical correction points x Number of gradual correction points 4096 (k) CSC_HINT[7:2] and CSC_VINT[7:2] (sub addresses: 00Bh and 00Ch) These set the correction interval for the horizontal and vertical directions of the color shading correction block in 6 bits. This setting has a setting range from 32 to 256 dots (lines) and can be set in 4-dot (-line) units. Set the "correction interval/4 - 1" value. HDIN VDIN Correction start position CSC_HP 1 1 2 3 4 5 6 7 8 Number of correction points CSC_HNUM 9 Correction start position CSC_VP 2 3 4 Color shading correction range 5 Number of correction points CSC_VNUM 6 7 Correction interval CSC_VINT - 75 - Correction interval CSC_HINT CXD3511AQ (l) CSC_HOS[7:2] and CSC_VOS[7:2] (sub addresses: 00Dh and 00Eh) These set the range for which virtual corrections are to be made. The same data as at the edge of the correction area for color shading correction is assumed for outside the correction area. It is possible to independently set values from 0 to 256 dots (lines) for the horizontal and vertical directions in 4-dot (-line) units. HDIN VDIN Correction start position CSC_HP Virtual correction range CSC_HOS Correction start position CSC_VP : Area actually corrected : Area virtually corrected (m) CSC_GNUM [2:0] (sub address: 006h) This sets the number of correction points in the gradual direction for color shading correction. It is possible to set 1 to 8 points. Set the "number of correction points - 1" value. (n) CSC_RGP1 to 8[9:1], CSC_GGP1 to 8[9:1] and CSC_BGP1 to 8[9:1] (sub addresses: 00Fh to 026h) These set the correction points for color shading correction in the gradual direction in 2-gradual units independently for each R, G and B signal. Registers are set in order of lowest number beginning from 3FFh. Always keep this order in mind when setting data. 3FFh Same data as Correction Point 1 CSC_R (G, B) GP1 300h CSC_R (G, B) GP2 CSC_R (G, B) GP3 200h CSC_R (G, B) GP4 CSC_R (G, B) GP5 CSC_R (G, B) GP6 100h CSC_R (G, B) GP7 CSC_R (G, B) GP8 000h Same data as Correction Point 8 - 76 - Virtual correction range CSC_VOS Color shading correction range CXD3511AQ (o) CSC_RGD1 to 8, CSC_GGD1 to 8 and CSC_BGD1 to 8 (sub addresses: 00Fh to 026h) These set to expand data set in RAM for color shading correction by 8bits by shifting data 1 bit in the MSB direction. This setting can be made independently for correction points in the gradual direction for each R, G and B signal. Setting value: 1 = Expand by 8 bits; 0 = Not expanded (p) CSC_XH (sub address: 006h) This sets the cross hatch display ON/OFF used during color shading correction. Setting value: 1 = Display; 0 = Not displayed (q) CSC_XH_DAT (sub address: 027h) This sets the display level (gradual level) of the cross hatch pattern used for color shading correction in 2-gradual units, 9 bits. (r) GC_ON (sub address: 02Bh) This sets the ghost cancel block processing ON/OFF. Setting value: 1 = Ghost cancel ON, 0 = Ghost cancel OFF (s) GC_MODE (sub address: 02Bh) This sets the signal processing period of ghost cancel block. Setting value: 1 = 24-dot period, 0 = 12-dot period (t) R_GC_LMT_DAT[9:0], G_GC_LMT_DAT[9:0] and B_GC_LIM_DAT[9:0] (sub addresses: 028h to 02Ah) These set the limiter data of the R, G and B ghost cancel block in 10 bits. (u) R_GC_ATT[7:0], G_GC_ATT[7:0] and B_GC_ATT[7:0] (sub addresses: 02Bh to 02Dh) These set the multiplier arithmetic coefficient of the R, G and B ghost cancel block in 8 bits. (v) RGT_SEL_ON, DLY_ON, DLY_DWN, DLY_R_RGT, DLY_G_RGT and DLY_B_RGT (sub address: 02Eh) These are the selectable delay line block settings. RGT_SEL_ON: This sets ON/OFF for port switching linked with right/left inversion. Setting value: 1 = ON, 0 = OFF DLY_ON: This sets the dot/line inverted drive support ON/OFF. Setting value: 1 = ON, 0 = OFF DLY_DWN: This sets the up/down inversion for the selectable delay line block. Setting value: 1 = Reflects the TG block DWN setting, 0 = Reflects the inverse of the TG block DWN setting DLY_R_RGT, DLY_G_RGT and DLY_B_RGT: These set the right/left inversion for the selectable delay line block. Setting value: 1 = Reflects the TG block RGT setting, 0 = Reflects the inverse of the TG block RGT setting - 77 - CXD3511AQ (w) OFFSET_ON (sub address: 02Eh) This sets the processing ON/OFF for the cycle offset block. Setting value: 1 = offset processing ON, 0 = offset processing OFF (x) OFFSET_MODE[1:0] (sub address: 02Eh) This sets the counter period for the cycle offset block. Setting value: 0h = 6-dot period, 1h = 12-dot period, 2h = 24-dot period (y) R_OFFSET1 to 12[4:0], G_OFFSET1 to 12[4:0] and B_OFFSET1 to 12[4:0] (sub addresses: 02Fh to 052h) These set the offset data for the cycle offset block in 5 bits with code. - 78 - 5-6. Pattern Generator Block (Main Address: 012h) The pattern generator block data format is as follows. Data Initial value PDAT7 PDAT0 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h PG_SIG2B[9:0] PG_G_ON PG_B_ON PG_HSTP[11] PG_HWST[11] PG_HWSTP[11] PG_VST[10] PG_HST[10:1] PG_HSTP[10:1] PG_HWST[10:1] PG_HWSTP[10:1] PG_VST[9:0] PG_VSTP[9:0] PG_VWST[9:0] PG_VWSTP[9:0] PG_STEP[9:1] PG_WIDTH[9:0] PG_SIG1R[9:0] PG_SIG2R[9:0] PG_SIG1G[9:0] PG_SIG2G[9:0] PG_SIG1B[9:0] PG_R_SEL PG_G_SEL PG_B_SEL PG_PAT[2:0] PG_VSTP[10] PG_VWST[11] PG_VWSTP[11] PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 Sub address PDAT9 PDAT8 000h PG_ON PG_R_ON 001h PG_STRP_SW PG_STAIR_SW PG_HST[11] 002h 003h 004h 005h 006h 007h 008h - 79 - 009h 00Ah -- 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h --: Don't care CXD3511AQ CXD3511AQ The detailed setting contents are described below. (a) PG_ON (sub address: 000h) This sets the test signal output ON/OFF. Setting value: 1 = Test pattern output mode enabled, 0 = Normal signal output (b) PG_R (G, B)_ON (sub address: 000h) These set the test signal level setting ON/OFF. Setting value: 1 = Various settings enabled, 0 = Output fixed to "0" (c) PG_R (G, B)_SEL (sub address: 000h) These switch the pattern and non-pattern signal levels within the effective area. Setting value: 1 = Pattern signal level is PG_SIG1R (G, B), 0 = Pattern signal level is PG_SIG2R (G, B) (d) PG_PAT[2:0] (sub address: 000h) This switches the display pattern within the window area. Setting value: See the table below. 0 1 2 3 4 5 6 7 Raster Window Vertical stripe/diagonal stripe Horizontal stripe Cross hatch Dot Horizontal ramp/horizontal stair Vertical ramp/vertical stair (e) PG_STRP_SW (sub address: 001h) (Valid only when PG_PAT[2:0] = 2h) This switches between vertical stripe and diagonal stripe. Setting value: 1 = Diagonal stripe, 0 = Vertical stripe (f) PG_STAIR_SW (sub address: 001h) (Valid only when PG_PAT[2:0] = 6h or 7h) This switches between ramp and stair. Setting value: 1 = Stair, 0 = Ramp (g) PG_HST[11:1] (sub addresses: 001h and 002h) PG_HSTP[11:1] (sub addresses: 001h and 003h) These set the horizontal effective area in 11 bits. The area can be set in 2-dot units using the front edge of the HDIN input as the reference. Set the "(set point - 66)/2" value. - 80 - CXD3511AQ (h) PG_HWST[11:1] (sub addresses: 001h and 004h) PG_HWSTP[11:1] (sub addresses: 001h and 005h) These set the horizontal window area in 11 bits. The area can be set in 2-dot units using the front edge of the HDIN input as the reference. Set the "(set point - 68)/2" value. (i) PG_VST[10:0] (sub addresses: 001h and 006h) PG_VSTP[10:0] (sub addresses: 001h and 007h) These set the vertical effective area in 11 bits. The area can be set in 1-line units using the front edge of the VDIN input as the reference. Set the "set point - 3" value. (j) PG_VWST[10:0] (sub addresses: 001h and 008h) PG_VWSTP[10:0] (sub addresses: 001h and 009h) These set the vertical window area in 11 bits. The area can be set in 1-line units using the front edge of the VDIN input as the reference. Set the "set point - 4" value. HDIN VDIN PG_HST PG_VST PG_HWST PG_HWSTP PG_HSTP Effective area PG_VWST Window area PG_VWSTP PG_VSTP (k) PG_STEP[9:1] (sub address: 00Ah) (Valid for PG_PAT[2:0] = 2h, 3h, 4h, and 5h) This sets the vertical stripe, diagonal stripe, horizontal stripe, cross hatch and dot period in 9 bits. The period can be set in 2-dot units. Set the "(period - 2)/2" value. (l) PG_WIDTH[9:0] (sub address: 00Bh) (Valid for PG_PAT[2:0] = 2h, 3h, 4h, and 5h) This sets the vertical stripe, diagonal stripe, horizontal stripe, cross hatch and dot line width in 10 bits. The width can be set in 1-dot units. Set the "width" value. (m) PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] (sub addresses: 00Ch to 011h) These set the output signal level inside and outside the pattern area within the effective area in 10 bits. The level can be set with an accuracy of 1 bit. - 81 - CXD3511AQ Notes on Handling * The power supply and GND patterns have a large effect on undesired radiation on the substrate and interference to analog circuits, etc. General precautions are as follows. * Make the GND pattern as wide as possible. Using a multi-layer substrate and a solid ground is recommended. * Connect each power supply pin to GND via a ceramic chip capacitor of 0.1F or more located as close to each pin as possible. * Do not use this IC under conditions other than the recommended operating conditions. * Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. * This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. * Since this IC utilizes a MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, interface with two power supplies of another circuit, or the order in which power is supplied to circuits. Make a thorough study of measures against the possibility of latch up before use. * When the initialization of this IC is performed at power-on, system clear cancellation is performed after the supply voltage is set in the range of the recommended operating conditions and stabilized. Keep in mind that the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply voltage is set in the range of the recommended operating conditions. * When designing the substrate, take sufficient care for the surrounding temperature and heat radiation, and make sure the IC junction temperature does not exceed the maximum value. * Be sure to make the number of dot clocks input to the CXD3511AQ in 1H an even number. Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate properly. * Be sure to make a thorough evaluation of any items not listed in this data sheet. - 82 - CXD3511AQ Application Circuit CTRL From A/D converter +3.3V 10 0.1 Auxiliary pulse To S/H driver To LCD panel To LCD panel To D/A converter +2.5V 0.1 0.1 0.1 0.1 0.1 10 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 R2OUT9 R1OUT8 DCK1X DCK2X TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 ENBR VCKR HCK1 DCK1 DCK2 XFRP XRGT DENB R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 HCK2 SHST VSTR CTRL VSTL HD1 PO5 PO4 PRG FRP PCG DWN VCKL ENBL RGT HD2 BLK PO1 PO2 PO3 HST CLP PST VSS VSS VSS VSS VSS VSS VDD2 VDD1 VDD1 VDD1 VDD2 VDD2 VSS VDD2 0.1 181 R1IN2 182 R1IN1 183 R1IN0 184 R2IN7 185 R2IN6 0.1 186 VDD2 187 VSS 188 R2IN5 189 R2IN4 190 R2IN3 191 R2IN2 192 R2IN1 193 R2IN0 194 G1IN7 195 G1IN6 196 G1IN5 0.1 197 VDD1 198 VSS 199 G1IN4 200 G1IN3 201 G1IN2 202 G1IN1 203 G1IN0 From A/D converter R1OUT7 120 R1OUT6 119 R1OUT5 118 R1OUT4 117 R1OUT3 116 VSS 115 VDD2 114 R1OUT2 113 R1OUT1 112 R1OUT0 111 R2OUT9 110 R2OUT8 109 R2OUT7 108 R2OUT6 107 R2OUT5 106 R2OUT4 105 R2OUT3 104 R2OUT2 103 VSS 102 VDD1 101 VDD2 100 0.1 0.1 R2OUT1 99 R2OUT0 98 G1OUT9 97 G1OUT8 96 G1OUT7 95 G1OUT6 94 G1OUT5 93 G1OUT4 92 G1OUT3 91 VSS 90 VDD1 89 G1OUT2 88 G1OUT1 87 G1OUT0 86 G2OUT9 85 VDD2 84 G2OUT8 83 G2OUT7 82 G2OUT6 81 G2OUT5 80 G2OUT4 79 VSS 78 VDD1 77 G2OUT3 76 G2OUT2 75 G2OUT1 74 G2OUT0 73 B1OUT9 72 B1OUT8 71 B1OUT7 70 B1OUT6 69 B1OUT5 68 VSS 67 VDD2 66 B1OUT4 65 B1OUT3 64 B1OUT2 63 B1OUT1 62 B1OUT0 61 0.1 0.1 0.1 0.1 To D/A converter 204 G2IN7 205 G2IN6 206 G2IN5 207 G2IN4 208 G2IN3 0.1 209 VDD1 210 VSS 211 G2IN2 212 G2IN1 213 G2IN0 214 B1IN7 215 B1IN6 216 B1IN5 217 B1IN4 218 B1IN3 219 B1IN2 220 B1IN1 0.1 221 VDD1 222 VSS 223 B1IN0 224 B2IN7 225 B2IN6 226 B2IN5 227 B2IN4 228 B2IN3 229 B2IN2 230 B2IN1 231 B2IN0 232 R1OSD1 233 R1OSD0 0.1 234 VDD2 235 VSS 236 G1OSD1 237 G1OSD0 238 B1OSD1 239 B1OSD0 CLKSEL1 CLKSEL2 G2OSD1 G2OSD0 CLKOUT R2OSD1 R2OSD0 B2OSD1 B2OSD0 B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 B2OUT5 B2OUT6 B2OUT7 B2OUT8 OSD input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 10 B2OUT9 240 YM1 YS1 PLLDIV XCLR1 XCLR2 XCLR3 PDAT9 PDAT8 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 CLKC CLKN PCLK CLKP PCTL HDIN VDIN VDD2 VDD2 VDD1 VDD1 VDD1 VDD2 VDD1 VDD2 YM2 YS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS 10 0.1 GND OSD input +3.3V 0.1 0.1 0.1 0.1 0.1 0.1 Parallel data input To D/A converter CLKOUT CLKN CLKP 10k 10k 10k HDIN1 VDIN1 +3.3V CLKC 1 1 1 CLKSEL1 CLKSEL2 GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 83 - PLLDIV GND CXD3511AQ Package Outline Unit: mm 240PIN QFP (PLASTIC) 34.6 0.2 32.0 0.1 180 181 121 0.10 120 4.1 MAX + 0.10 0.40 - 0.15 A 240 1 0.5 + 0.05 0.22 - 0.03 60 0.08 M 61 + 0.05 0.145 - 0.03 0 to 8 DETAIL A SONY CODE EIAJ CODE JEDEC CODE 0.45 MIN - 0.75 MAX 0.25 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 7.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS QFP-240P-L022 QFP240-P-3232 LEAD SPECIFICATIONS ITEM LEAD MATERIAL LEAD TREATMENT SPEC. COPPER ALLOY Sn-Bi - 84 - Sony Corporation |
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